Provided are an overlay mark, and an overlay measurement method and a semiconductor device manufacturing method using the overlay mark. Specifically, provided is an overlay mark for determining relative misalignment between two or more pattern layers or between two or more patterns separately formed in one pattern layer, the overlay mark including a first overlay mark positioned in the center, a second overlay mark positioned above and below the first overlay mark or on the left and right thereof, and a third overlay mark and a fourth overlay mark each positioned in a diagonal line with the first overlay mark in between.

Systems and methods for in-die metrology using target design patterns are provided. These systems and methods include selecting a target design pattern based on design data representing the design of an integrated circuit, providing design data indicative of the target design pattern to enable design data derived from the target design pattern to he added to second design data, wherein the second design data is based on the first design data. Systems and methods can further include causing structures derived from the second design data to be printed on a wafer, inspecting the structures on the wafer using a charged-particle beam tool, and identifying metrology data or process defects based on the inspection. In some embodiments the systems and methods further include causing the charged-particle beam tool, the second design data, a scanner, or photolithography equipment to be adjusted based on the identified metrology data or process defects.

A product includes at least one semiconductor substrate, multiple thin-film layers disposed on the at least one substrate, and an overlay target formed in at least one of the thin-film layers. The overlay target includes a first sub-target having a first center of symmetry and including first target features having a first linewidth, and a second sub-target having a second center of symmetry coincident with the first center of symmetry and including second target features, which have a second linewidth, greater than the first linewidth, and are adjacent to but non-overlapping with the first target features.

The present application provides a mask applied to semiconductor photolithography and a photolithographic method, and the mask includes at least one pattern group, each pattern group including at least one light-transmitting region and at least one shielding region, the light-transmitting regions and the shielding regions being arranged at intervals, and after exposure, each pattern group forming an independent mark on a wafer. The present application has the following advantages. The independent mark formed on the wafer according to the mask has the same shape as a contour of a pattern of the mask, and does not have a pattern defect, which improves accuracy of an independent mark pattern formed on the wafer, and then alignment precision of the semiconductor photolithography as well as overlaying accuracy in a following semiconductor process, thus increasing a quality and a yield of products.

The application provides a structure for an alignment measurement mark and a method for an alignment measurement, and includes a first overlay mark and a second overlay mark. The second overlay mark includes a pattern structure to be measured. A layer where the first overlay mark is located is adjacent to a layer where the second overlay mark is located. An orthographic projection of the first overlay mark onto the layer where the second overlay mark is located is located at an inner side of the second overlay mark, or an orthographic projection of the first overlay mark onto the layer where the second overlay mark is located is located at a periphery of the second overlay mark.

A method of pattern alignment is provided. The method includes identifying a reference pattern positioned below a working surface of a wafer. The wafer is exposed to a first pattern of actinic radiation. The first pattern is a first component of a composite pattern. The first pattern of actinic radiation is aligned using the reference pattern. The wafer is exposed to a second pattern of actinic radiation. The second pattern is a second component of the composite pattern and exposed adjacent to the first pattern. The second pattern of actinic radiation is aligned with the first pattern of actinic radiation using the reference pattern.

A method for manufacturing a semiconductor device may include: forming a first layer comprising a plurality of patterns, each pattern having a different respective pitch; performing exposure and development to form a second layer at a layer different from the first layer; determining whether a pitch shift of a part of exposure patterns formed is within a tolerance range, using a Moire pattern; and performing etching for the second layer when the pitch shift of the part of exposure patterns is determined to be within the tolerance range. Performing the exposure and the development may include forming a first exposure pattern corresponding to a key pattern having a first pitch, forming a second exposure pattern corresponding to a cell pattern having a second pitch, and forming a third exposure pattern corresponding to a middle pitch pattern having a third pitch between the first pitch and the second pitch.

According to one embodiment, a registration mark includes a first step portion and a second step portion. The first step portion includes a plurality of first steps which descend step by step in a first direction from a surface of a substrate or a layer formed on the substrate. The second step portion includes a plurality of second steps which descend step by step from the surface in a second direction different from the first direction and have the same number as the number of the plurality of first steps, is spaced apart from the first step portion, and is disposed rotationally symmetrically to the first step portion.

A semiconductor structure includes a device area that includes a first structure in a first layer having a top surface above a top surface of the first layer, and a second structure in a second layer on top of the first layer, where the first structure is pinned in the second structure; an overlay metrology area for optically evaluating an overlay error between the second and first structure, including: a third structure in the first layer, having a top surface above the top surface of the first layer, a fourth structure in the second layer, where the combination of the third and fourth structures mimics the combination of the first structure and the second structures, and a fifth structure in the first layer, for use as a reference structure.

Methods of inspecting photomasks are provided. A method of inspecting a photomask includes electronically inspecting a first mask pattern in a mask region of the photomask and refraining from electronically inspecting a separate second mask pattern in the mask region of the photomask. The first mask pattern includes a geometric feature that corresponds to at least a portion of the second mask pattern. Moreover, the mask region is outside of a scribe lane region of the photomask. Related methods of manufacturing photomasks and methods of manufacturing semiconductor devices are also provided.