G06F1/3228

Data Management For Efficient Low Power Mode Handling In A Storage Device

A method and apparatus for identifying data that is to be accessible in a low power state of a data storage device, and store this data in a physical (or logical) block that will be accessible in a low power state of the data storage device. Low power accessible data may be identified by host metadata of the data, indicating access is needed in a low power state. In other embodiments, the data storage device may learn the power state in which data should be accessible. In these embodiments, a controller stores information regarding the power state of a namespace in which the data is stored as an indicator to make the data accessible in a low power state. Alternatively, the controller stores a previous power state in which the data was accessed as an indicator to make the data accessible in a low power state.

Multi-Mode Integrated Circuits With Balanced Energy Consumption
20220382360 · 2022-12-01 ·

Aspects of the disclosure include methods, systems, and apparatus, including computer-readable storage media for multi-mode integrated circuits with balanced energy consumption. A method includes determining, by one or more processors and based at least on a maximum energy threshold for planned multi-mode system having one or more processing units, a respective number of operations that can be performed per clock cycle by the processing units for each operating mode. The system is configured to consume the same amount of energy per clock cycle in each operating mode, but perform more operations in operating modes corresponding to operations performed on smaller bit-width operands.

Performance mode control method and electronic device supporting same

An embodiment of the present invention comprises: a communication module for communicating with at least one external device; a microphone for receiving a user utterance; a memory for storing performance mode information having been configured in the electronic device; and a processor electrically connected to the communication module, the microphone, and the memory, wherein the processor is configured to: receive, through the microphone, a second user utterance associated with task execution; transmit first data associated with the second user utterance to an external device; receive, from the external device, second data associated with at least a part of processing of the first data; identify a first work load allocated to the electronic device at the time of receiving the second data; and compare a second work load required for processing the second data and the first work load, so as to control the performance mode. In addition, various embodiments recognized through the specification are possible.

State suspension for optimizing start-up processes of autonomous vehicles

Diagnostics and boot up for AV hardware and software of a computer system of an autonomous vehicle may be performed based at least on receiving a shutdown or power off indication, then a computing state of the computer system may be suspended with the computer system entering a low-power mode. The suspended computing state can be rapidly restored without requiring a reboot and diagnostics for key-on. To ensure the integrity of the saved computing state, the computer system may exit the low-power mode, rerun the diagnostics, reload the programs, and then reenter the low-power mode. Restoring the suspended computing state may be triggered by a user inserting an ignition key, pressing a button to turn on the vehicle, opening a door to the vehicle, remotely unlocking the vehicle, remotely starting the vehicle, etc.

INTEGRATED CIRCUIT, DYNAMIC VOLTAGE AND FREQUENCY SCALING (DVFS) GOVERNOR, AND COMPUTING SYSTEM INCLUDING THE SAME

Disclosed is an integrated circuit, which counts parameters required for a dynamic voltage frequency scaling (DVFS) operation. The integrated circuit includes: an event block accessing a bus, which connects processing devices to each other, and outputting an event signal, based on data transmitted through the bus; a clock counter counting the number of clock signals received from a clock management unit; a plurality of performance counters respectively counting parameters used to calculate a workload, based on the event signal; an interface receiving an operation signal from the DVFS governor, which determines an operation frequency and an operation voltage of a processing device based on the workload, and transmitting the number of clock signals and the parameters to the DVFS governor; and a controller controlling operations of the event block, the clock counter, and the plurality of performance counters, based on the operation signal.

Noise shielding circuit and chip

A chip includes a processor, a memory, and a storage controller of the memory. There is an access path between the processor and the storage controller, and the processor reads data from or writes data into the memory by using the storage controller through the access path. The chip further includes a shielding circuit. The shielding circuit is configured to shield a signal on the access path when the processor is powered off.

Neural network operational method and apparatus, and related device

The present disclosure describes methods, devices, and storage mediums for adjusting computing resource. The method includes obtaining an expected pooling time of a target pooling layer and a to-be-processed data volume of the target pooling layer; obtaining a current clock frequency corresponding to at least one computing resource unit used for pooling; determining a target clock frequency according to the expected pooling time of the target pooling layer and the to-be-processed data volume of the target pooling layer; and in response to that the convolution layer associated with the target pooling layer completes convolution and the current clock frequency is different from the target clock frequency, switching the current clock frequency of the at least one computing resource unit to the target clock frequency, and performing pooling in the target pooling layer based on the at least one computing resource unit having the target clock frequency.

Gesture-triggered augmented-reality
11592907 · 2023-02-28 · ·

A user may routinely wear or hold more than one computing devices. One of the computing devices may be a head-mounted computing-device configured for augmented reality. The head-mounted computing-device may include a camera. While imaging, the camera can consume power and processing resources that diminish a battery of the head-mounted computing device. To improve a battery life and to enhance a user's privacy, imaging of the camera can be deactivated during periods when the user is not interacting with the head-mounted computing device and activated when the user wishes to interact with the head-mounted computing device. The activation of the camera can be triggered by gestured data collected by a computing device other than the head-mounted computing-device.

System and method of operating an information handling system

In one or more embodiments, one or more systems, one or more methods, and/or one or more processes may determine that a platform reset signal from a processor of an information handling system has been asserted; may determine that a power conservation state from the processor was not asserted within an amount of time; may determine that an operating system restart occurred; may notify a hardware root of trust device to authenticate information handling system firmware; may assert a resume reset signal to the processor; may authenticate the information handling system firmware; may de-assert a power OK signal to the processor; may remove power from the processor; may determine that the resume reset signal to the processor is de-asserted and that the processor is out of the power conservation state; and may provide power to the processor.

System and method of operating an information handling system

In one or more embodiments, one or more systems, one or more methods, and/or one or more processes may determine that a platform reset signal from a processor of an information handling system has been asserted; may determine that a power conservation state from the processor was not asserted within an amount of time; may determine that an operating system restart occurred; may notify a hardware root of trust device to authenticate information handling system firmware; may assert a resume reset signal to the processor; may authenticate the information handling system firmware; may de-assert a power OK signal to the processor; may remove power from the processor; may determine that the resume reset signal to the processor is de-asserted and that the processor is out of the power conservation state; and may provide power to the processor.