Patent classifications
G06F1/3228
Wearable Device for Creating Social Distancing Awareness
A wearable device for creating social distancing awareness is disclosed. The wearable device may include a sensor unit, an output unit, and a control unit connected to the sensor unit and the output unit. The sensor unit may detect one or more objects within a predetermined distance from a user wearing the wearable device. The control unit may control the output unit to generate one or more alerts for a predetermined time period, in response to detecting the one or more objects. The output unit may generate the one or more alerts for creating the social distancing awareness.
Method of task transition between heterogenous processors
A method, system, and apparatus determines that one or more tasks should be relocated from a first processor to a second processor by comparing performance metrics to associated thresholds or by using other indications. To relocate the one or more tasks from the first processor to the second processor, the first processor is stalled and state information from the first processor is copied to the second processor. The second processor uses the state information and then services incoming tasks instead of the first processor.
Selective hibernation of activities in an electronic device
In an electronic device capable of running multiple software applications concurrently, applications, documents, cards, or other activities can be selected for hibernation so as to free up system resources for other activities that are in active use. A determination is made as to which activities should hibernate, for example based on a determination as to which activities have not been used recently or based on relative resource usage. When an activity is to hibernate, its state is preserved on a storage medium such as a disk, so that the activity can later be revived in the same state and the user can continue with the same task that was being performed before the activity entered hibernation.
Chip frequency modulation method and apparatus of computing device, hash board, computing device and storage medium
The invention provides a chip frequency modulation method and apparatus of a computing device, a hash board, a computing device and a storage medium. The chip frequency modulation method comprises: setting a plurality of working frequencies for the operational chip and causing the plurality of cores work at the respective working frequencies; analyzing a computing performance indicator of each core at its current working frequency; and modulating the current working frequency of the core up or down according to the computing performance indicator of the core modulating the frequency of a core with high computing performance up and modulating the frequency of a core with low computing performance down. Therefore, the invention can automatically modulate a frequency corresponding to each core according to the actual computing performance of each core in the operational chip of the computing device, thereby maximizing the computing performance of the cores.
Chip frequency modulation method and apparatus of computing device, hash board, computing device and storage medium
The invention provides a chip frequency modulation method and apparatus of a computing device, a hash board, a computing device and a storage medium. The chip frequency modulation method comprises: setting a plurality of working frequencies for the operational chip and causing the plurality of cores work at the respective working frequencies; analyzing a computing performance indicator of each core at its current working frequency; and modulating the current working frequency of the core up or down according to the computing performance indicator of the core modulating the frequency of a core with high computing performance up and modulating the frequency of a core with low computing performance down. Therefore, the invention can automatically modulate a frequency corresponding to each core according to the actual computing performance of each core in the operational chip of the computing device, thereby maximizing the computing performance of the cores.
Information processing apparatus including controller capable of communicating with connected external apparatus and shifting to power-saving state, and control method therefor
According to one embodiment, an information processing apparatus includes a universal serial bus (USB) controller capable of shifting to a low-power state and configured to transmit data with a predetermined pattern to a personal computer (PC) when the USB controller is recovered from the low-power state. The information processing apparatus includes a hardware logic configured to cause the USB controller to shift to the low-power state, a reading unit configured to read an image formed on a document according to a reading instruction, and a physical layer (PHY) configured to transmit, to the PC, image data on the document with the image read by the reading unit. The information processing apparatus prohibits the USB controller from shifting to the low-power state during a period in which the PHY transmits the image data to the PC.
Method and apparatus for controlling hardware device, electronic device and storage medium
Disclosed are a method and apparatus for controlling a hardware module, electronic device and storage medium. In an embodiment of the present disclosure, the method may include: timing a waiting state of the hardware module to obtain a current waiting duration of the hardware module when it enters a first waiting state; generating an interrupt signal based on the current waiting duration; determining program information corresponding to the current waiting duration under triggering from the interrupt signal; executing an action corresponding to the program information for the hardware module, and controlling it to enter a second waiting state. In the present disclosure, the hardware module is controlled to execute actions corresponding to different programs based on different waiting durations through an interrupt mechanism, thus controlling the hardware module to switch between waiting states with different power consumption, and achieving a good balance between energy saving and performance.
Power allocation management for external storage
The present disclosure generally relates to power management for an external storage device. The external storage device includes a power allocation unit coupled to an array of memory devices. A single bridge is present to provide a connection to a host device. The memory devices have operational power states that utilize a first amount of power and non-operational power states that utilize a second amount of power that is less than the first amount of power. The power allocation unit changes the power state of the individual memory devices between operational and non-operational based upon need, but also ensures that the external storage device does not exceed the total power allocation. Thus, the power allocation unit may change a power state of one memory device from operational to non-operational in order to change the power state of another memory device from non-operational to operational.
Power allocation management for external storage
The present disclosure generally relates to power management for an external storage device. The external storage device includes a power allocation unit coupled to an array of memory devices. A single bridge is present to provide a connection to a host device. The memory devices have operational power states that utilize a first amount of power and non-operational power states that utilize a second amount of power that is less than the first amount of power. The power allocation unit changes the power state of the individual memory devices between operational and non-operational based upon need, but also ensures that the external storage device does not exceed the total power allocation. Thus, the power allocation unit may change a power state of one memory device from operational to non-operational in order to change the power state of another memory device from non-operational to operational.
Intelligent prediction of processor idle time apparatus and method
A machine-learning (ML) scheme running a software driver stack to learn user habits of entry into low power states, such as Modern Connect Standby (ModCS), and duration depending on time of day, and/or system telemetry. The ML creates a High Water Mark (HWM) number of dirty cache lines (DL) as a hint to a power agent. A power agent algorithm uses these hints and actual system's number of DL to inform the low power state entry decision (such as S0i4 vs. S0i3 entry decision) for a computing system.