Described are systems and methods for power management. A processing system includes one or more cores and a connected power management unit (PMU). The PMU is selected from one of: a first level PMU which can power scale a; a second level PMU which can independently control power from a shared cluster power supply to each core of two or more cores in a cluster; a third level PMU where each core includes a power monitor which can track power performance metrics of an associated core; and a fourth level PMU when a complex includes multiple clusters and each cluster includes a set of the one or more cores, the fourth level PMU including a complex PMU and a cluster PMU for each of the multiple clusters, the complex PMU and cluster PMUs provide two-tier power management. Higher level PMUs include power management functionality of lower level PMUs.

Power governance circuitry is provided to control a performance level of a processing unit of a processing platform. The power governance circuitry comprises measurement circuitry to measure a current utilization of the processing unit at a current operating frequency and to determine any change in utilization or power and frequency control circuitry is provided to update the current operating frequency to a new operating frequency by determining a new target quantified power expenditure to be applied in a subsequent processing cycle depending on the determination of any change in utilization or power. A new operating frequency is selected to satisfy the new target quantified power based on a scalability function specifying a variation of a given value of utilization or power with the operating frequency. A processing platform and machine readable instructions are provided to set a new quantified target power of a processing unit.

A digital value obtained from a preceding circuit element is temporarily stored and made available for a subsequent circuit element at a controlled moment of time. The digital value is received through a data input. A triggering signal is also received, a triggering edge of which defines an allowable time limit before which a digital value must be available at said data input to become available for said subsequent circuit element. Between first and second pulse-enabled subregister stages, an internal digital value from the first pulse-enabled subregister stage and information of the changing moment of said digital value at the data input in relation to said allowable time limit are used to ensure passing a valid internal digital value to the second pulse-enabled subregister stage. Said second pulse-enabled subregister stage makes said valid internal digital value available for said subsequent circuit element. A timing event observation signal is output as an indicator of said digital value at said data input having changed within a time window that begins at said allowable time limit and is shorter than one cycle of said triggering signal.

A low power sensing device includes a sensor including key sensors configured to generate sensing signals, respectively, a reference sensor configured to generate a reference sensing signal, a two-state clock generator configured to generate a first clock signal and a second clock signal having clock frequencies different from each other, and a controller. The controller is configured to receive the sensing signals and the reference sensing signal, control enable operations and disable operations of the sensor and the reference sensor based on a first operation mode and a second operation mode each repeatedly performed for a predetermined time, receive the first clock signal during the first operation mode, and receive the second clock signal during the second operation mode.

A low power sensing device includes a sensor including key sensors configured to generate sensing signals, respectively, a reference sensor configured to generate a reference sensing signal, a two-state clock generator configured to generate a first clock signal and a second clock signal having clock frequencies different from each other, and a controller. The controller is configured to receive the sensing signals and the reference sensing signal, control enable operations and disable operations of the sensor and the reference sensor based on a first operation mode and a second operation mode each repeatedly performed for a predetermined time, receive the first clock signal during the first operation mode, and receive the second clock signal during the second operation mode.

A system for computing devices includes a central processing unit (CPU that is configured to perform in a plurality of power modes, each power mode being pre-defined to have a different code-execution performance capability than remaining ones of the plurality of power modes. The system further includes a sampling peripheral, an electrical output, and a memory device. The memory device is configured to select and execute a specific module from the plurality of modules based on the context-identifying input triggering the specific module. If triggered, each module is executed to receive the context-identifying input from the sampling peripheral, and to operate the CPU in a dedicated power mode of the plurality of power modes.

A hardware architecture for an artificial neural network ANN. The ANN includes a consecutive series made up of an input layer, multiple processing layers, and an output layer. Each layer maps a set of input variables onto a set of output variables, and output variables of the input layer and of each processing layer are input variables of the particular layer that follows in the series. The hardware architecture includes a plurality of processing units. The implementation of each layer is split among at least two of the processing units, and at least one resettable switch-off device is provided via which at least one processing unit is selectively deactivatable, independently of the input variables supplied to it, in such a way that at least one further processing unit remains activated in all layers whose implementation is contributed to by this processing unit.

In one embodiment, a processor includes a power controller having a resource allocation circuit. The resource allocation circuit may: receive a power budget for a first core and at least one second core and scale the power budget based at least in part on at least one energy performance preference value to determine a scaled power budget; determine a first maximum operating point for the first core and a second maximum operating point for the at least one second core based at least in part on the scaled power budget; determine a first efficiency value for the first core based at least in part on the first maximum operating point for the first core and a second efficiency value for the at least one second core based at least in part on the second maximum operating point for the at least one second core; and report a hardware state change to an operating system scheduler based on the first efficiency value and the second efficiency value. Other embodiments are described and claimed.

Examples are disclosed that relate to allocating power to peripheral device interfaces. One example provides, at a computing device, a method, comprising obtaining a measurement of power consumption by one or more peripheral devices, and based at least on the measurement and on a maximum power tolerance of a power source, allocating to each respective interface a minimum portion of power output from the power source. The method further comprises rendering a remainder of the maximum power tolerance available for consumption by one or more processors, the remainder including the maximum power tolerance minus a sum of the minimum portions, where the remainder and a system portion of power output are available for consumption by the one or more processors, and where a performance attribute of the one or more processors is not throttled while total power consumption does not exceed a threshold power output from the power source.

The present embodiment relates to a touch power management circuit and a touch driving system including the same, and more particularly, to a touch power management circuit that prevents unnecessary power consumption during a pen touch driving period in order to reduce power consumption of a display device, and a touch driving system including the same.