Systems and methods are disclosed for processor power management using instruction throttling. For example, an integrated circuit may include a processor core including a processor pipeline configured to execute instructions; a register configured to store a power dial value that indicates a portion of available clock cycles for throttling of instruction flow through the processor pipeline; and an instruction throttling circuit configured to periodically stall removal of instructions from a queue in the processor pipeline for a number of clock cycles that is determined based on the power dial value.

Power governance circuitry is provided to control a performance level of a processing unit of a processing platform. The power governance circuitry comprises measurement circuitry to measure a current utilization of the processing unit at a current operating frequency and to determine any change in utilization or power and frequency control circuitry is provided to update the current operating frequency to a new operating frequency by determining a new target quantified power expenditure to be applied in a subsequent processing cycle depending on the determination of any change in utilization or power. A new operating frequency is selected to satisfy the new target quantified power based on a scalability function specifying a variation of a given value of utilization or power with the operating frequency. A processing platform and machine readable instructions are provided to set a new quantified target power of a processing unit.

Power governance circuitry is provided to control a performance level of a processing unit of a processing platform. The power governance circuitry comprises measurement circuitry to measure a current utilization of the processing unit at a current operating frequency and to determine any change in utilization or power and frequency control circuitry is provided to update the current operating frequency to a new operating frequency by determining a new target quantified power expenditure to be applied in a subsequent processing cycle depending on the determination of any change in utilization or power. A new operating frequency is selected to satisfy the new target quantified power based on a scalability function specifying a variation of a given value of utilization or power with the operating frequency. A processing platform and machine readable instructions are provided to set a new quantified target power of a processing unit.

A mobile device allows transmission of additional outgoing application data requests in response to occurrence of receipt of data transfer from a remote entity, user input in response to a prompt displayed to the user, and a change in a background status of an application executing on the mobile device. Additional outgoing application data requests are foreground application requests.

A request to perform a compute task is received. A plurality of compute processor resources eligible to perform the compute task is identified, wherein the plurality of compute processor resources includes two or more of the following: a field-programmable gate array, an application-specific integrated circuit, a graphics processing unit, or a central processing unit. Based on an optimization metric, one of the compute processor resources is dynamically selected to perform the compute task.

Exemplary embodiments provide thermal wear spreading among a plurality of thermal die regions in an integrated circuit or among dies by using die region wear-out data that represents a cumulative amount of time each of a number of thermal die regions in one or more dies has spent at a particular temperature level. In one example, die region wear-out data is stored in persistent memory and is accrued over a life of each respective thermal region so that a long term monitoring of temperature levels in the various die regions is used to spread thermal wear among the thermal die regions. In one example, spreading thermal wear is done by controlling task execution such as thread execution among one or more processing cores, dies and/or data access operations for a memory.

One example method includes performing, in an edge device that includes a power source, operations including monitoring a running process and obtaining, based on the monitoring, power consumption information associated with the running process, adjusting, based on the power consumption information, a priority of the running process, and providing, to an entity, the power consumption information and/or information concerning the priority of the running process.

One example method includes performing, in an edge device that includes a power source, operations including monitoring a running process and obtaining, based on the monitoring, power consumption information associated with the running process, adjusting, based on the power consumption information, a priority of the running process, and providing, to an entity, the power consumption information and/or information concerning the priority of the running process.

An application processor includes an application processor including a first processor configured to generate a control signal based on whether user data is changed, wherein the application processor is configured to implement a power manager which dynamically controls power provided to the first processor, in response to the control signal.

An application processor includes an application processor including a first processor configured to generate a control signal based on whether user data is changed, wherein the application processor is configured to implement a power manager which dynamically controls power provided to the first processor, in response to the control signal.