A storage device includes non-volatile memory, a storage controller including a first controller processor connected to the non-volatile memory, and a second controller processor connected to the non-volatile memory, and shared memory to store a mapping table. The shared memory may be connected to the first controller processor and the second controller processor to share mapping table information between the first controller processor and the second controller processor. The storage controller may set a power mode of the first controller processor and the second controller processor based on an input/output intensity.

A method for off-loading tasks between a set of wireless earpieces in an embodiment of the present invention may have one or more of the following steps: (a) monitoring battery levels of the set of wireless earpieces, (b) determining the first wireless earpiece battery level and the second wireless battery level, (c) communicating the battery levels of each wireless earpiece to the other wireless earpiece of the set of wireless earpieces, (d) assigning a first task involving one or more of the following: computing tasks, background tasks, audio processing tasks, and sensor data analysis tasks from one of the set of wireless earpieces to the other wireless earpiece if the battery level of the one of the set of wireless earpieces falls below a critical threshold, (e) communicating data for use in performing a second task to the other wireless earpiece if the second task is communicated to the first wireless earpiece.

A method for off-loading tasks between a set of wireless earpieces in an embodiment of the present invention may have one or more of the following steps: (a) monitoring battery levels of the set of wireless earpieces, (b) determining the first wireless earpiece battery level and the second wireless battery level, (c) communicating the battery levels of each wireless earpiece to the other wireless earpiece of the set of wireless earpieces, (d) assigning a first task involving one or more of the following: computing tasks, background tasks, audio processing tasks, and sensor data analysis tasks from one of the set of wireless earpieces to the other wireless earpiece if the battery level of the one of the set of wireless earpieces falls below a critical threshold, (e) communicating data for use in performing a second task to the other wireless earpiece if the second task is communicated to the first wireless earpiece.

A local power control arbiter is provided to interface with a global power control unit of a processing platform having a plurality of processing entities. The local power control arbiter controls a local processing unit of the processing platform. The local power arbiter has an interface to receive from the global power control unit, a local performance limit allocated to the local processing unit depending on a global power control evaluation and processing circuitry to determine any change to one or more processing conditions prevailing in the local processing unit on a timescale shorter than a duration for which the local performance limit is applied to the local processing unit by the global power control unit and to select a performance level for the local processing unit depending on both the local performance limit and the determined change, if any, to the prevailing processing conditions on the local processing unit.

A local power control arbiter is provided to interface with a global power control unit of a processing platform having a plurality of processing entities. The local power control arbiter controls a local processing unit of the processing platform. The local power arbiter has an interface to receive from the global power control unit, a local performance limit allocated to the local processing unit depending on a global power control evaluation and processing circuitry to determine any change to one or more processing conditions prevailing in the local processing unit on a timescale shorter than a duration for which the local performance limit is applied to the local processing unit by the global power control unit and to select a performance level for the local processing unit depending on both the local performance limit and the determined change, if any, to the prevailing processing conditions on the local processing unit.

Systems and methods increase computational efficiency in machine learning accelerators. In embodiments, this is accomplished by evaluating, partitioning, and selecting computational resources to uniquely process, accumulate, and store data based on the type of the data and configuration parameters that are used to process the data. Various embodiments, take advantage of the zeroing feature of a Built-In Self-Test (BIST) controller to cause a BIST circuit to create a known state for a hardware accelerator, e.g., during a startup and/or wakeup phase, thereby, reducing data movements and transitions to save both time and energy.

Systems and methods increase computational efficiency in machine learning accelerators. In embodiments, this is accomplished by evaluating, partitioning, and selecting computational resources to uniquely process, accumulate, and store data based on the type of the data and configuration parameters that are used to process the data. Various embodiments, take advantage of the zeroing feature of a Built-In Self-Test (BIST) controller to cause a BIST circuit to create a known state for a hardware accelerator, e.g., during a startup and/or wakeup phase, thereby, reducing data movements and transitions to save both time and energy.

An integrated circuit includes; a core configured to process an instruction in accordance with a voltage-frequency level, an instruction complexity calculation circuit configured to calculate an instruction complexity for at least one instruction to-be-processed after a reference time in relation to heating information related to the core acquired before the reference time, wherein the instruction complexity calculation circuit is further configured to generate a control signal corresponding to the instruction complexity, and a dynamic voltage and frequency scaling (DVFS) controller configured to adjust the voltage-frequency level after the reference time in response to the control signal.

Systems and methods for managing a power budget are provided. The method includes designating, by a power budget manager implemented on at least one processor, each of one or more applications with an individual quality of service (QoS) designation, the one or more applications executable by the at least one processor, assigning, by the power budget manager, a throttling priority to each of the one or more applications based on the individual QoS designations, determining, by the power budget manager, whether a platform mitigation threshold is exceeded, and responsive to determining that the platform mitigation threshold is exceeded, throttling, by the power budget manager, processing power allocated to at least one application of the one or more applications based on the throttling prioritization.

A data processing system comprises a hybrid processor comprising a big TPU and a small TPU. At least one of the TPUs comprises an LP of a processing core that supports SMT. The hybrid processor further comprises hardware feedback circuitry. A machine-readable medium in the data processing system comprises instructions which, when executed, enable an OS in the data processing system to collect (a) processor topology data from the hybrid processor and (b) hardware feedback for at least one of the TPUs from the hardware feedback circuitry. The instructions also enable the OS to respond to a determination that a thread is ready to be scheduled by utilizing (a) an OP setting for the ready thread, (b) the processor topology data, and (c) the hardware feedback to make a scheduling determination for the ready thread. Other embodiments are described and claimed.