An eyewear device that includes a plurality of SoCs that share processing workload, and a USB port configured to perform low-power debugging and automation of the plurality of SoCs, such as using either a Universal Asynchronous Receiver-Transmitter (UART) or a Serial Wire Debug (SWD). The eyewear includes a USB hub configured such that the USB port can simultaneously communicate with the plurality of SoCs. The USB hub can be shut down to disable the USB hub, and all the SoCs can enter their low-power modes without being kept awake by a persistent USB connection. The eyewear includes a first switch and a control logic, wherein the control logic controls the first switch and enables the USB port to perform low-power debugging and automation of the SoCs. The eyewear further includes a second switch, wherein the control logic controls the second switch to enable the USB port to perform low-power debugging and automation of the SoCs via a processor, or to enable the USB port to control each of the SoCs.

Methods and systems for performing current sense compensation for one or more power stages in a multiphase voltage regulator are described. A controller can be connected to a plurality of power stages through a communication interface. The controller can generate a data packet including a command to obtain temperature information and an address that identifies a specific power stage among the plurality of power stages. The controller can send the data packet to the plurality of power stages using the communication interface. The controller can receive temperature information of the specific power stage from the specific power stage through the communication interface. The controller can compensate a sensed current of the specific power stage based on the received temperature information of the specific power stage.

Methods and systems for performing current sense compensation for one or more power stages in a multiphase voltage regulator are described. A controller can be connected to a plurality of power stages through a communication interface. The controller can generate a data packet including a command to obtain temperature information and an address that identifies a specific power stage among the plurality of power stages. The controller can send the data packet to the plurality of power stages using the communication interface. The controller can receive temperature information of the specific power stage from the specific power stage through the communication interface. The controller can compensate a sensed current of the specific power stage based on the received temperature information of the specific power stage.

A computer-implemented method of controlling power consumption in a multi-processor computing device comprises: determining whether a first processor is operating in a high-power regime or a low-power regime; selecting a first set of control rules that includes a first subset of control rules that apply when the first processor is operating in the high-power regime and a second subset of control rules that apply when the first processor is operating in the low-power regime; determining one or more power settings for the first processor based on the first set of control rules; and causing the first processor to perform one or more operations based on the one or more power settings.

An integrated circuit includes a first, second and third power rail, and a header circuit coupled to a gated circuit. The gated circuit is configured to operate on a first or second voltage. The first and second power rail are on a back-side of a wafer, and extend in a first direction. The header circuit is configured to supply the first voltage to the gated circuit by the first power rail. The second power rail is separated from the first power rail in a second direction. The second power rail is configured to supply the second voltage to the gated circuit. The third power rail is on a front-side of the wafer and includes a first set of conductors extending in the second direction, and separated in the first direction. Each of the first set of conductors is configured to supply a third voltage to the header circuit.

An application processor includes an application processor including a first processor configured to generate a control signal based on whether user data is changed, wherein the application processor is configured to implement a power manager which dynamically controls power provided to the first processor, in response to the control signal.

An application processor includes an application processor including a first processor configured to generate a control signal based on whether user data is changed, wherein the application processor is configured to implement a power manager which dynamically controls power provided to the first processor, in response to the control signal.

In various examples, permanent faults in hardware component(s) and/or connections to the hardware component(s) of a computing platform may be predicted before they occur using in-system testing. As a result of this prediction, one or more remedial actions may be determined to enhance the safety of the computing platform (e.g., an autonomous vehicle). A degradation rate of a performance characteristic associated with the hardware component may be determined, detected, and/or computed by monitoring values of performance characteristics over time using fault testing.

In various examples, permanent faults in hardware component(s) and/or connections to the hardware component(s) of a computing platform may be predicted before they occur using in-system testing. As a result of this prediction, one or more remedial actions may be determined to enhance the safety of the computing platform (e.g., an autonomous vehicle). A degradation rate of a performance characteristic associated with the hardware component may be determined, detected, and/or computed by monitoring values of performance characteristics over time using fault testing.

Disclosed is an electronic device. The electronic device includes a battery, a charging part configured to be connectable to an external charging device to charge the battery, a memory, and a processor operatively connected to the charging part and the memory. The processor may determine whether the charging part is connected to the external charging device, determine whether the electronic device moves and/or electronic device usage time information of a user, and reduce a voltage at which the battery enters supplementary charging to a second voltage lower than a first voltage which corresponds to a value stored in the memory, based on whether the electronic device moves and/or the electronic device usage time information. In addition, it is possible to implement various other embodiments understood through the disclosure.