An electronic device is provided. The electronic device includes: a display device including a plurality of light-emitting elements for displaying an optical image on a front side of the display device; an illumination element integrated into the display device and configured to emit light for illuminating a scene in front of the front side of the display device; an optical sensor configured to sense reflections of the light from the scene; an optical transmitter configured to transmit an optical control signal encoded with control information for controlling light emission by the illumination element; and an optical receiver integrated into the display device and configured to receive the optical control signal and generate an electrical control signal based on the optical control signal. The electronic device further includes a driver circuit integrated into the display device and configured to drive the illumination element based on the electrical control signal.

Processor-based systems employing local dynamic power management based on controlling performance and operating power consumption, and related methods. The processor-based system is configured to locally manage its power consumption by dynamically adjusting operating frequency and/or operating voltage of power supplied to the processor-based system. The processor-based system includes a power control circuit that is aware of the overall power budget for the processor-based system. The control processor in the processor-based system can dynamically increase the voltage level of the power supplied to the processor-based system and/or the operating frequency if the consumed power is lower than the power budget. The power control circuit can also dynamically decrease the operating frequency and/or the voltage level of the power supplied to the processor-based system if the consumed power is higher than the power budget.

A method of an electronic device are provided in which current consumption for one or more components of the electronic device is compared with a predetermined current. A first surface temperature of the electronic device is determined based on the comparison and power consumption of the one or more components. A location is detected where heat corresponding to the first surface temperature is generated. A second surface temperature of the electronic device is obtained based on power consumption of a component disposed in the electronic device corresponding to the location where the heat is generated. A target temperature is set based on the obtained second surface temperature. The component is controlled to reduce the power consumption of the component based on the target temperature.

A method of an electronic device are provided in which current consumption for one or more components of the electronic device is compared with a predetermined current. A first surface temperature of the electronic device is determined based on the comparison and power consumption of the one or more components. A location is detected where heat corresponding to the first surface temperature is generated. A second surface temperature of the electronic device is obtained based on power consumption of a component disposed in the electronic device corresponding to the location where the heat is generated. A target temperature is set based on the obtained second surface temperature. The component is controlled to reduce the power consumption of the component based on the target temperature.

A peak power management (PPM) system is provided for managing peak power operations between two or more NAND memory dies. The PPM system includes a PPM circuit on each NAND memory die. Each PPM circuit includes a first pull-up driver electrically connected to a first power source and a first end of a PPM resistor; a second pull-up driver electrically connected to a second power source and a second end of the PPM resistor; a pull-down driver electrically connected to the second end of the PPM resistor; and a PPM contact pad connected to the second end of the PPM resistor. The PPM contact pads of the two or more NAND memory dies are electrically connected with each other with a common electric potential. The PPM system is configured to manage peak power operations according to the electric potential of the PPM contact pads.

A single communication fabric for a data processing apparatus is provided. The fabric has an interconnection network to provide a topology of data communication channels between a plurality of data-handling functional units. The interconnection network has a first interconnection domain to provide data communication between a first subset of the data-handling functional units and a second interconnection domain to provide data communication between a second subset of the data-handling functional units. The power management circuitry is arranged to control a first performance level for the first interconnection domain independently from control of a second performance level for the second interconnection domain. Machine readable instructions and a method are provided to concurrently set performance levels of two different fabric domains to respective different operating frequencies.

An operational circuit of a virtual currency data processing device includes: at least two operational chip groups (31) configured to operate within respective operating voltage threshold ranges of the operational chip groups (31) to receive a communication signal which includes an issued task, perform calculations according to the issued task, and transmit a communication signal which includes a calculation result; a control module (32) configured to operate within an operating voltage threshold range of the control module (32) to transmit the communication signal which includes the issued task and receive the communication signal which includes the calculation result; at least two signal forwarding and electrical isolation modules, each of which is communicatively connected to the control module and a respective operational chip group and is configured to forward communication signals between the control module and the respective operational chip group, and isolate an operating voltage threshold of the operational chip groups from an operating voltage threshold of the control module to make the operational chip groups and the control module capable of identifying communication signals sent by each other.

An operational circuit of a virtual currency data processing device includes: at least two operational chip groups (31) configured to operate within respective operating voltage threshold ranges of the operational chip groups (31) to receive a communication signal which includes an issued task, perform calculations according to the issued task, and transmit a communication signal which includes a calculation result; a control module (32) configured to operate within an operating voltage threshold range of the control module (32) to transmit the communication signal which includes the issued task and receive the communication signal which includes the calculation result; at least two signal forwarding and electrical isolation modules, each of which is communicatively connected to the control module and a respective operational chip group and is configured to forward communication signals between the control module and the respective operational chip group, and isolate an operating voltage threshold of the operational chip groups from an operating voltage threshold of the control module to make the operational chip groups and the control module capable of identifying communication signals sent by each other.

A system on chip (SoC) includes a first core and a second core, first and second power gating switches, and a first power switch. The first power gating switch is arranged between the first core and a first power rail that receives a first voltage, and is selectively turned on in response to a first power gating signal. The second power gating switch is arranged between the second core and a second power rail that receives a second voltage, and is selectively turned on in response to a second power gating signal. The first power switch is arranged between the first power rail and the second power rail, and is selectively turned on in response to a first power control signal to connect the first power gating switch or the second power gating switch both the first power rail and the second power rail.

A system on chip (SoC) includes a first core and a second core, first and second power gating switches, and a first power switch. The first power gating switch is arranged between the first core and a first power rail that receives a first voltage, and is selectively turned on in response to a first power gating signal. The second power gating switch is arranged between the second core and a second power rail that receives a second voltage, and is selectively turned on in response to a second power gating signal. The first power switch is arranged between the first power rail and the second power rail, and is selectively turned on in response to a first power control signal to connect the first power gating switch or the second power gating switch both the first power rail and the second power rail.