A computer system supports measuring execution time of concurrent threads. A thread allocates a timing buffer in thread local storage. During execution, the thread also has access to a system timer which it can sample with microsecond or better precision with a single instruction. For any sequence of instructions within the thread for which execution time is to be measured, the sequence of instructions has an identifier and includes two commands, herein called a start command and an end command. The start command samples the system timer to obtain a start time, and stores the identifier and the start time in the timing buffer in the thread local storage. The end command samples the system timer to obtain an end time, and updates the data for the corresponding identifier in the timing buffer, to indicate an elapsed time for execution of the sequence of instructions. The start command and end command each can be implemented as a single executable instruction.

In one example, a method includes allocating separate portions of memory for a control stack and a data stack. The method also includes, upon detecting a call instruction, storing a first return address in the control stack and a second return address in the data stack; and upon detecting a return instruction, popping the first return address from the control stack and the second return address from the data stack and raising an exception if the two return addresses do not match. Otherwise, the return instruction returns the first return address. Additionally, the method includes executing an exception handler in response to the return instruction detecting an exception, wherein the exception handler is to pop one or more return addresses from the control stack until the return address on a top of the control stack matches the return address on a top of the data stack.

Embodiments of the present invention provide a memory resource optimization method and apparatus, relate to the computer field, solve a problem that existing multi-level memory resources affect each other, and optimize an existing single partitioning mechanism. A specific solution is: obtaining performance data of each program in a working set by using a page coloring technology, obtaining a category of each program in light of a memory access frequency, selecting, according to the category of each program, a page coloring-based partitioning policy corresponding to the working set, and writing the page coloring-based partitioning policy to an operating system kernel, to complete corresponding page coloring-based partitioning processing. The present invention is used to eliminate or reduce mutual interference of processes or threads on a memory resource in light of a feature of the working set, thereby improving overall performance of a computer.

Nonsequential readahead for deep learning training that includes: receiving an indication of a list of batch storage locations for a batch of data objects; prefetching, for each storage location in the list of batch storage locations, storage content corresponding to the batch of data objects; and storing the storage content corresponding to the batch of data objects within a cache accessible to an artificial intelligence workflow.

A memory controller controls a memory device including memory blocks, and can equalize wear levels of cores for controlling memory devices. The memory controller includes: cores for controlling the zones; a reset information controller for generating reset count values representing a number of reset requests input with respect to the zones, in response to a reset request, and generating reset count sum values obtained by summing reset count values of zones controlled by each of the cores; and a wear level manager for controlling the cores such that a core that is different from a first core having a highest reset count sum value from among the cores controls some of zones controlled by the first core according to whether a difference value between the highest reset count sum value and a lowest reset count sum value from among the reset count sum values exceeds a threshold difference value.

Some examples describe data locality solutions for a hyperconverged computing system. In an example, a data request may be received at a Virtual Storage Appliance (VSA) node amongst a plurality of VSA nodes in a hyperconverged computing system. A determination may be made whether a remapped logical block address (LBA) associated with the data request is included on a first mapping layer on the VSA node. In response to a determination that the remapped LBA associated with the data request is present on the first mapping layer of the VSA node, the remapped LBA may be used to resolve the data request. In response to a determination that the remapped LBA associated with another data request is not present on the first mapping layer of the VSA node, a second mapping layer on the VSA node may be used to resolve the other data request.

Techniques are provided for multi-tier write allocation. A storage system may store data within a multi-tier storage environment comprising a first storage tier (e.g., storage devices maintained by the storage system), a second storage tier (e.g., a remote object store provided by a third party storage provider), and/or other storage tiers. A determination is made that data (e.g., data of a write request received by the storage system) is to be stored within the second storage tier. The data is stored into a staging area of the first storage tier. A second storage tier location identifier, for referencing the data according to a format utilized by the second storage tier, is assigned to the data and provided to a file system hosting the data. The data is then destaged from the staging area into the second storage tier, such as within an object stored within the remote object store.

A processing apparatus includes a memory, a processor, and a setting processor. The memory has plural memory areas, and the plural memory areas include registered memory areas that are registered to be used, and unregistered memory areas that are not registered to be used. The processor stores input data in a corresponding memory area among the plural memory areas. In response to an instruction to perform a setting process related to a function which uses a memory area, the setting processor executes a setting process including registering a memory area selected from among the unregistered memory areas to use the selected memory area for the function or including presenting the selected memory area to a user as a candidate for the memory area used by the function.

Information identifying a current hardware configuration of a system may be received. Furthermore, information of a new hardware component that has not been installed may be received. A graphical user interface (GUI) may be provided with an option to install the new hardware component with the system. In response to a selection from the GUI of the option to install the new hardware component with the system, a plurality of actions to install the new hardware component with the current hardware configuration of the system may be determined. A guide may be generated based on the determined plurality of actions.

A method of resizing a block storage volume for a virtual machine includes executing the virtual machine and attaching a virtual storage device to the virtual machine. The virtual storage device exposes the block storage volume on memory hardware to the virtual machine. The block storage volume includes a first storage capacity. The method also includes mounting the block storage volume to the virtual machine and resizing the block storage volume while the virtual machine continues to execute. The block storage volume is resized without attaching an additional virtual storage device to the virtual machine or mounting an additional block storage volume to the virtual machine.