A memory interface for interfacing with a memory device includes a control circuit configured to determine whether a trigger event has occurred for initializing one or more memory locations in the memory device, and initialize the one or more memory locations in the memory device with pre-defined data upon determining the trigger event has occurred.

Techniques for determining a data tape read quality value are disclosed. A data tape system generates a value representing a quality of a data tape based on attributes of the data tape. The system calculates the data quality value using an algorithm based on: (a) a particular data tape error correction value, (b) data tape length value representing a length of data tape traversed during data-processing operations, and (c) a scaling factor. The scaling factor is based on a relationship between the particular data tape error correction value and a rate of degradation of the data tape. The scaling factor may be generated by applying a trained machine learning model to attributes of a data tape. The model generates a scaling factor for a particular data tape based on the attributes of the particular data tape.

According to the embodiments, an external storage device switches to an interface controller for supporting only a read operation of nonvolatile memory when a shift condition for shifting to a read only mode is met. A host device switches to an interface driver for supporting only the read operation of the nonvolatile memory when determining to recognize as read only memory based on information acquired from the external storage device.

A flash memory initialization method executed by a flash memory initialization device to initialize a flash memory device having a flash memory and a flash memory controller includes: determining an acceptable maximum number N of candidate addresses; determining a number M of different capacity sizes; classifying the candidate addresses into M portions; determining a difference value between two address values of any two adjacent addresses among the m-th portion of candidate addresses; determining multiple address values of the m-th portion of candidate addresses according to the difference value; and determining actual addresses of the m-th portion of candidate addresses according to the multiple address values; and controlling the flash memory controller to write the boot up information into at least one storage location corresponding to at least one of the m-th portion of candidate addresses according to the actual addresses.

A data storage device is disclosed comprising a non-volatile storage medium (NVSM), and control circuitry configured to receive a plurality of access commands, process the plurality of access commands using a customer prediction model to predict a customer of the data storage device, wherein the customer prediction model is trained off-line based on access patterns of a plurality of different customers. The control circuitry then configures access to the NVSM based on the predicted customer.

Methods, apparatus, and processor-readable storage media for automatically adjusting storage system configurations in a storage-as-a-service environment using machine learning techniques are provided herein. An example computer-implemented method includes obtaining performance-related data for at least one storage system in a storage-as-a-service environment; processing at least a portion of the obtained performance-related data using one or more rule-based analyses; identifying, based at least in part on results of the processing, one or more storage system configurations, of the at least one storage system, requiring adjustment; determining, using at least one machine learning technique, one or more adjustment amounts for the one or more storage system configurations; and automatically adjusting the one or more storage system configurations, within the storage-as-a-service environment, in accordance with the one or more determined adjustment amounts.

Devices and techniques for an adjustable watchdog in a memory device are disclosed herein. A memory operation command is received at a first time with a memory device from a host. A reset signal is received, with the memory device from the host, at a second time following the first time. A time interval between the first time and the second time is measured. A delay interval for a timer in the memory device to reset the memory device independently of receiving a further reset signal from the host is established based on the measured time interval.

Examples implementations relate to configuration of computational drives. An example computational drive includes a housing to be inserted in a drive bay of a host device, and persistent storage. The computational drive may also include a processor to respond to an insertion of the housing into the drive bay of the host device by configuring the computational drive to operate as a new node of a distributed file system, and connecting the computational drive to the distributed file system as the new node.

A system includes a memory array and control logic, operatively coupled to the memory array, to perform operations including causing, during chip initialization, a first attempt of a chip initialization process to be performed based on a first configuration. The first configuration includes a first set of control settings for reading a block of the memory array during the first attempt. The operations further include determining that the first attempt has failed, and, in response to determining that the first attempt has failed, causing an automatic chip initialization retry process to be performed. Causing the automatic chip initialization retry process to be performed includes causing a second attempt of the chip initialization process to be performed using a second configuration. The second configuration includes a second set of control settings different from the first set of control settings for reading the block during the second attempt.

A method, computer program product, and computing system for receiving a re-initialization operation request for a storage array, the storage array including a plurality of self-encrypting drives. A reversion state may be determined for each self-encrypting drive of the plurality of self-encrypting drives. In response to determining that at least one self-encrypting drive is in an unreverted state, at least one predefined reversion key for reverting the at least one self-encrypting drive from a predefined area of the storage array may be accessed. Each self-encrypting drive of the plurality of self-encrypting drives in the unreverted state may be reverted to a reverted state using the at least one predefined reversion key.