A hybrid memory system provides rapid, persistent byte-addressable and block-addressable memory access to a host computer system by providing direct access to a both a volatile byte-addressable memory and a volatile block-addressable memory via the same parallel memory interface. The hybrid memory system also has at least a non-volatile block-addressable memory that allows the system to persist data even through a power-loss state. The hybrid memory system can copy and move data between any of the memories using local memory controllers to free up host system resources for other tasks.

Systems and methods are described for a cross-site high availability distributed storage system. According to one embodiment, a computer implemented method includes providing a remote direct memory access (RDMA) request for a RDMA stream, and generating, with an interconnect (IC) layer of the first storage node, multiple IC channels and associated IC requests for the RDMA request. The method further includes mapping an IC channel to a group of multiple transport layer sessions to split data traffic of the IC channel into multiple packets for the group of multiple transport layer sessions using an IC transport layer of the first storage node and assigning, with the IC transport layer, a unique transaction identification (ID) to each IC request and assigning a different data offset to each packet of a transport layer session.

Systems and methods for an interconnect layer send queue reservation system are provided. In one example, a method involves performing a transfer of data (e.g., an NVLog) from a storage system to a secondary storage system. A send queue having a fixed number of slots is maintained within an interconnect layer interposed between a file system and a Remote Direct Memory Access (RDMA) layer of the storage system. The interconnect layer implements an application programming interface (API) for the reservation system. A deadlock situation is avoided by, during a suspendable phase of a write transaction, making a reservation for slots within the send queue via the reservation system for the transfer of data. When the reservation is successful, the write transaction proceeds with a modify phase, during which the reservation is consumed and the interconnect layer is caused to perform an RDMA operation to carry out the transfer of data.

The present disclosure includes apparatuses and methods related to data transfer in memory. An example apparatus can include a first number of memory devices coupled to a host via a first number of ports and a second number of memory devices coupled to the first number of memory device via a second number of ports, wherein a first number of commands are executed to transfer data between the first number of memory devices and the host via the first number of ports and a second number of commands are executed to transfer data between the first number of memory device and the second number of memory device via the second number of ports.

Memory bank remapping based on sensed temperatures of a memory device can provide an overall reduced power consumption of the memory device. Signaling indicative of sensed temperatures detected by a plurality of temperature sensors within a stack of memory dies of a memory device can be received by address circuitry of the memory device. Based on the sensed temperatures and respective positions of the temperature sensors within the stack of memory dies, a portion of the memory device experiencing an excessive operating temperature can be identified. Logical addresses of a first memory bank of a memory die of the stack of memory dies near or at least partially within the identified portion can be remapped to physical addresses of a second memory bank of the memory die that is further away from the identified portion than the first memory bank.

A data storage change is received for a piece of data, wherein the data storage change is from a first location to a second location. Two or more possible paths to perform the data storage change are determined. A plurality of weights for each path of the two or more paths is determined. A weighted transfer time for each path of the two or more paths is determined.

An apparatus comprises at least one processing device. The at least one processing device is configured to obtain storage-side performance information maintained by a storage system in conjunction with processing of input-output operations directed to the storage system by a host device over a network, to dynamically select a particular one of a plurality of distinct load balancing policies available in the host device based at least in part on the obtained storage-side performance information, and to apply the selected load balancing policy in directing additional input-output operations from the host device to the storage system. At least one of the load balancing policies comprises a storage cache aware load balancing policy that causes different ones of the input-output operations to be directed to different cache entities of he storage system based at least in part on cache-related performance metrics of the obtained storage-side performance information.

A semiconductor device includes a relay chip configured to be connected to a host; a first chip connected to the relay chip via a first channel; and a second chip connected to the relay chip via a second channel. The relay chip is configured to receive, from the host, a first enable signal for selecting the first channel and a second enable signal for selecting the second channel. During a first period in which the first enable signal is maintained at a non-active level and the second enable signal is maintained at an active level, the relay chip is configured to perform, in parallel, a first data transfer operation via the first channel and a first command issuing operation via the second channel.

A storage device is provided including a memory controller having a neural processing unit (NPU); a first nonvolatile memory (NVM) connected to the memory controller through a first channel; and a second NVM connected to the memory controller through a second channel. The first NVM stores first weight data for the NPU and the second stores second weight data for the NPU. The memory controller is configured to determine one of the first and second channels that is less frequently accessed upon receiving an inference request from the neural processor, and access a corresponding one of the first weight data and the second weight data using the determined one channel.

A control device switching method includes obtaining, by a first control device, configuration information of a logical unit number (LUN) from a second control device coupled to the first control device, where the LUN is created in a storage device and is accessed by a host through the second control device, providing, by the first control device, a first path to the host based on the configuration information, where the first path is for the host to access the LUN using the first control device, notifying, by the first control device, the second control device to set a second path to be faulty, and switching, by the first control device, a path for the host to access the LUN from the second path to the first path. The second path is for the host to access the LUN using the second control device.