Patent classifications
G06F3/0652
ELECTRONIC DEVICE AND REMOTE CONTROL SYSTEM
A computer includes an SMS module that communicates with a management server apparatus via a network, a display that displays predetermined information, and a CPU that controls an operation of the display. When the SMS module receives a control command from the management server apparatus via the network, the CPU executes processing corresponding to the control command. Furthermore, the CPU transmits a notification signal including information, which indicates a state of execution of the control program, to the management server apparatus via the network.
Furthermore, the CPU displays, on the display, a state indicator including information which indicates a state of execution of the control program when the notification signal cannot be transmitted to the management server apparatus via the network.
METHOD AND APPARATUS FOR MANAGING STORAGE DEVICE
A storage management method and a storage management apparatus are provided. In some embodiments, the method includes: detecting, during a preset length of time, a writing amount per time unit of service data of a target network service in a target storage; retrieving a correspondence relationship between the writing amount per time unit and an amount of a redundant storage, wherein the relationship indicates the amount of the redundant storage increases with the increasing of the writing amount per time unit; determining a first amount of the redundant storage corresponding to the first writing amount per time unit according to the correspondence relationship; and configuring the redundant storage for the target network service in accordance with the first amount of the redundant storage.
RECOVERING FREE SPACE IN NONVOLATILE STORAGE WITH A COMPUTER STORAGE SYSTEM SUPPORTING SHARED OBJECTS
To identify objects shared by entities and to, in turn, identify free space in nonvolatile storage, a computer system uses a probabilistic data structure which tests whether an element is a member of a set. Such probabilistic data structures are created for entities in the storage system that share objects. The probabilistic data structure for an entity represents the objects that are used by that entity. When an entity is deleted, each object used by that entity is compared to the probabilistic data structures of other entities to determine if there is a likelihood that the object is used by one or more of the other entities. If the likelihood determined for an object is above an acceptable threshold, then the object is not deleted. If the likelihood determined for an object is below the set threshold, then the object can be deleted and the corresponding storage locations can be marked as free.
Secrecy System And Decryption Method Of On-Chip Data Stream Of Nonvolatile FPGA
A secrecy system and a decryption method of on-chip data stream of nonvolatile FPGA are provided in the present invention. The nonvolatile memory module of the system is configured to only allow the full erase operation. After the full erase operation is finished, the nonvolatile memory module gets into the initial state. Only the operation to the nonvolatile memory module under the initial state is effective, and thereby the encryption region unit is arranged in the nonvolatile memory module. Only the decryption data written into the encryption region unit under the initial state can make the nonvolatile memory module to be readable, so that the decryption of the system is finished, which greatly improves the secrecy precision.
MITIGATING GC EFFECT IN A RAID CONFIGURATION
A system and method for managing garbage collection in Solid State Drives (SSDs) in a Redundant Array of Independent Disks (RAID) configuration, using a RAID controller is described. A control logic can control read and write requests for the SSDs in the RAID configuration. A selection logic can select an SSD for garbage collection. Setup logic can instruct the selected SSD to enter a garbage collection setup phase. An execute logic can instruct the selected SSD to enter and exit the garbage collection execute phase.
Memory controller and operating method thereof
A memory controller controls a memory device including memory blocks, and can equalize wear levels of cores for controlling memory devices. The memory controller includes: cores for controlling the zones; a reset information controller for generating reset count values representing a number of reset requests input with respect to the zones, in response to a reset request, and generating reset count sum values obtained by summing reset count values of zones controlled by each of the cores; and a wear level manager for controlling the cores such that a core that is different from a first core having a highest reset count sum value from among the cores controls some of zones controlled by the first core according to whether a difference value between the highest reset count sum value and a lowest reset count sum value from among the reset count sum values exceeds a threshold difference value.
Optimization of power usage of data storage devices
Systems, methods and apparatuses to control power usage of a data storage device. For example, the data storage device has a temperature sensor configured to measure the temperature of the data storage device are provided. A controller of the data storage device determines a set of operating parameters that identify an operating condition of the data storage device. An inference engine of the data storage device determines, using an artificial neural network in the data storage device and based on the set of operating parameters, an operation schedule for a period of time of processing input and output of the data storage device. The operation schedule is configured to optimize a performance of the data storage device in the period of time without the temperature of the data storage device going above a threshold.
Adjusting a preprogram voltage based on use of a memory device
A method is described that includes determining a number of program and erase cycles associated with a block of pages of a memory device and determining a preprogram voltage based on the number of program and erase cycles to apply to the block of pages prior to an erase operation. The method further includes applying the preprogram voltage to the block of pages and performing an erase operation on the block of pages following application of the preprogram voltage to the block of pages.
EDGE ACCELERATOR CARD
An edge accelerator card has a first interface, a second interface, a memory and a processor. The first interface is to couple to a server. The second interface is to couple to a storage system. The processor is to handle communication between the server and the storage system through the first interface and the second interface. The processor is to perform at least one task as directed by the storage system, using the memory and communication through at least the second interface.
SECURELY ARMING A MEMORY DEVICE FOR SELF-DESTRUCTION BY IMPLEMENTING A SELF-DESTRUCTION COUNTDOWN TIMER USING A BATTERY BACKED REAL-TIME CLOCK
A processing device receives a command to arm a memory device for self-destruction. In response to the command, a self-destruction countdown timer is commenced. An expiry of the self-destruction countdown timer and based on detecting the expiry of the self-destruction countdown timer, data stored by the memory device is destructed.