The present disclosure provides a neural network processor and neural network computation method that deploy a memory and a cache to perform a neural network computation, where the memory may be configured to store data and instructions of the neural network computation, the cache may be connected to the memory via a memory bus, thereby, the actual compute ability of hardware may be fully utilized, the cost and power consumption overhead may be reduced, parallelism of the network may be fully utilized, and the efficiency of the neural network computation may be improved.

An addition mask value generator is provided. A first operation circuit is configured to obtain first intermediate data according to first output mask value and fourth output mask value. A second operation circuit is configured to obtain the addition output mask value of a first mask group according to first intermediate data and fourth input mask value. A third operation circuit is configured to obtain second intermediate data according to second output mask value and third output mask value. A fourth operation circuit is configured to obtain the addition output mask value of a second mask group according to second intermediate data and second input mask value. The first and second addition input mask values of first mask group are first and second input mask values. The first and second addition input mask values of second mask group are third input mask value and first intermediate data.

An electronic device emulating nonvolatile memory includes: a first memory including a data block in which data is stored and a metadata block in which metadata relating to the data is stored; a second memory in which data to be used by the electronic device is stored; and a processor configured to manage data of the first memory and the second memory. The processor may generate a random value for distinguishing between first data and other data when the first data is stored in the first memory, include the random value in the first data and then store the first data in the data block, and store, in the second memory, a password value obtained by encrypting information on the first data based on the random value and a roll-back key.

Systems and techniques that facilitate Hamiltonian simulation based on simultaneous-diagonalization are provided. In various embodiments, a partition component can partition one or more Pauli operators of a Hamiltonian into one or more subsets of commuting Pauli operators. In various embodiments, a diagonalization component can generate one or more simultaneous-diagonalization circuits corresponding to the one or more subsets. In various aspects, a one of the one or more simultaneous-diagonalization circuits can diagonalize the commuting Pauli operators in a corresponding one of the one or more subsets. In various embodiments, an exponentiation component can generate one or more exponentiation circuits corresponding to the one or more subsets. In various aspects, a one of the one or more exponentiation circuits can exponentiate the simultaneously diagonalized commuting Pauli operators in a corresponding one of the one or more subsets. In various embodiments, a simulation component can concatenate the one or more simultaneous-diagonalization circuits, the one or more exponentiation circuits, and one or more adjoints of the one or more simultaneous-diagonalization circuits of the one or more subsets to simulate a time evolution of the Hamiltonian.

The invention presents a solution in which blockchain Transactions are created to implement the functionality of a logic gate. The invention may be implemented on the Bitcoin platform or an alternative blockchain platform. The transaction includes a locking script which comprises instructions selected so as to implement the functionality of a logic gate, such as the XOR gate. When the script is executed (because a second transaction is attempting to spend the output associated with the locking script) the inputs will be processed by the conditional instructions to provide an output of TRUE or FALSE. The inputs are pre-processed by one or more computing agents so that they are evaluated to TRUE or FASLE prior to being used as inputs to the script. The second transaction is transmitted to the blockchain network for validation and, if determined to be valid, it will be written to the blockchain. Validation of the second transaction can be interpreted as a TRUE output. Thus, the locking script of the first transaction provides the functionality of the desired logic gate. The invention provides numerous advantages and can be used in a wide variety of applications, such as for the implementation of control systems and unit.

Data structure and microcontroller architecture performing binary multiply-accumulate operations using multiple partial copies of weights. Destination-register location, source-register location, and weight-register location are received. Using the weight-register location, a sub-set of the weight bits is copied a select number of times based on a filter index value that is received. Each copy of the sub-set of weights is executed in parallel. Using the source-register location, a sub-set of the input bits is selected based on the size of the sub-set of weights, wherein the sub-set of input bits is shifted one bit from a previous sub-set of input bits. XOR operation is performed on each corresponding bit in the copy of the sub-set of weights with each corresponding bit in the selected sub-set of input bits. In a corresponding destination sub-location, output of each XOR operation is aggregated with each other and with current value of the corresponding destination sub-location.

An apparatus is provided for determining, for use in a tag-guarded memory, a selected tag value from a plurality of tag values. The apparatus comprises ordered list generation circuitry to receive an excluded tag vector comprising a plurality of fields, where each field is associated with a tag value and identifies whether the associated tag value is excluded from use. The ordered list generation circuitry is arranged to generate, from the excluded tag vector, an ordered list of non-excluded tag values. The apparatus further comprises count determination circuitry to determine, using the excluded tag vector and an identified start tag value, a count value indicative of a number of non-excluded tag values occurring in a region of the excluded tag vector bounded by an initial field and a field corresponding to the start tag value. The apparatus also comprises tag selection circuitry to determine the selected tag value from the ordered list based on the count value and an identified offset which indicates a required number of non-excluded tag values between the start tag value and the selected tag value.

A memory system, comprising: i) a first electronic device comprising a processor, ii) a second electronic device being external to the first electronic device and comprising a memory, wherein the memory stores a memory image over at least a part of a data set stored on the memory, and iii) a hash value related to the memory image. The first electronic device and the second electronic device are coupled such that the processor has at least partial control over the second electronic device. The processor is configured to, when updating the data set stored on the memory of the second electronic device, also update the hash value related to the memory image using an incremental hashing operation so that only those parts of the memory image are processed that have changed.

The disclosed embodiments are related to storing critical data in a memory device such as Flash or DRAM memory device. In one embodiment, a device comprising a plurality of parallel processors is disclosed, the plurality of parallel processors configured to: perform a search and match operation, the search and match operation loading a plurality of synaptic identifier bit strings and a plurality of spike identifier bit strings, the search and match operation further generating a plurality of bitmasks; perform a synaptic integration phase, the synaptic integration phase generating a plurality of synaptic current vectors based on the plurality of bitmasks, the synaptic current vectors associated with respective synthetic neurons; solve a neural membrane equation for each of the synthetic neurons; and update membrane potentials associated with the synthetic neurons, the membrane potentials stored in a memory device.

Disclosed is a mechanism implemented by a server. The mechanism comprises receiving a plurality of data points. Indications of logical operators, the plurality of data points, and function calls are transmitted to an administrator. Conditional commands describing event packages are received from the administrator. The conditional commands include correlations between the logical operators, the data points, and the function calls. The conditional commands are executed to build the event packages based on user information.