Techniques manage data of a Redundant Array of Independent Disks (RAID). Such techniques involve: obtaining a first parity of checksum pair, which is determined based on a first checksum when user data of data disks in the RAID are predetermined values; determining, based on current checksums of the data disks in the RAID, a second parity of checksum pair of the RAID, the first parity of checksum pair and the second parity of checksum pair respectively comprising a row parity of checksum and a diagonal parity of checksum; and determining, based on the first parity of checksum pair and the second parity of checksum pair, a third parity of checksum pair for updating parity data of parity disks of the RAID.

Embodiments of the present disclosure relate to establishing and verifying an index file. The method for establishing an index file includes: in response to receiving a data block to be stored, determining first verification information for verifying the data block and a first storage address for storing the data block. This method further includes: based on the first verification information, determining an index entry for the data block and a second storage address for storing the index entry, wherein the index entry includes the first verification information and the first storage address, and the index entry will be included in the index file. This method further includes: based on the index entry and the second storage address, determining second verification information. This method further includes: based on the second verification information and historical verification information for the index file, determining third verification information for verifying the index file.

Systems, methods, and apparatuses relating to performing logical operations on packed data elements and testing the results of that logical operation to generate a packed data resultant are described. In one embodiment, a processor includes a decoder to decode an instruction into a decoded instruction, the instruction having fields that identify a first packed data source, a second packed data source, and a packed data destination, and an opcode that indicates a bitwise logical operation to perform on the first packed data source and the second packed data source and indicates a width of each element of the first packed data source and the second packed data source; and an execution circuit to execute the decoded instruction to perform the bitwise logical operation indicated by the opcode on the first packed data source and the second packed data source to produce a logical operation result of packed data elements having a same width as the width indicated by the opcode, perform a test operation on each element of the logical operation result to set a corresponding bit in a packed data test operation result to a first value when any of the bits in a respective element of the logical operation result are set to the first value, and set the corresponding bit to a second value otherwise, and store the packed data test operation result into the packed data destination.

A programmable slave circuit on a communication bus is provided. In a non-limiting example, the communication bus can be a radio frequency front-end (RFFE) bus operating based on a master-slave topology and the programmable slave circuit can be an RFFE slave circuit on the RFFE bus. The programmable slave circuit is configured to receive a high-level command(s) (e.g., a macro word) over the communication bus. A processing circuit in the programmable slave circuit is programmed to generate a low-level command(s) (e.g., a bitmap word) for controlling a coupled circuit(s) based on the high-level command(s). In this regard, it is possible to program or reprogram the processing circuit, for example via over-the-air (OTA) updates, based on the high-level command(s) to be supported, thus making it possible to flexibly customize the programmable slave circuit according to operating requirements and configurations.

A non-volatile memory module in parallel architecture is described. It includes memory function and data storage function in a single module. It enables host system to use memory bus to access storage devices and to use the same memory command protocol for storage device access. The parallel architecture enables contents in memory devices and storage devices to be exchanged freely on module under the control of host memory controller to boost performance of computer and to retain data even if power to computer is shut off. The configuration of non-volatile memory module can be partitioned or expanded into multiple independent channels on module seamlessly with or without ECC supports.

The present disclosure generally relates to methods of operating storage devices. The storage device comprises a controller comprising first random access memory (RAM1), second random access memory (RAM2), and a storage unit divided into a plurality of zones. A first command to write data to a first zone is received, first XOR data is generated in the RAM1, and the data of the first command is written to the first zone. When a second command to write data to a second zone is received, the generated first XOR data is copied from the RAM1 to the RAM2, and second XOR data for the second zone is copied from the RAM2 to the RAM1. The second XOR data is updated with the second command, and the data of the second command is written to the second zone. The updated second XOR data is copied from the RAM1 to the RAM2.

This microprocessor is configured to compute a code C.sub.1, used to detect an execution fault, using a relationship C.sub.i=P o F.sub.α(D.sub.i), where: F.sub.α(D.sub.i)=E.sub.0 o . . . o E.sub.q o . . . o E.sub.NbE−1(D.sub.i), E.sub.q(x)=T.sub.αm,q o . . . o T.sub.αj,q o . . . o T.sub.α1,q o T.sub.α0,q(X), and T.sub.αj,q is a conditional transposition, configured by a secret parameter α.sub.j,q, that permutes two blocks of bits B.sub.2j+1,q and B.sub.2j,q of the variable x only when the parameter a.sub.j,q is equal to a first value, the blocks B.sub.2j+1,q and B.sub.2j,q of all of the transpositions T.sub.αj,q of the stage E.sub.q being different from one another and not overlapping and the blocks B.sub.2j+1,q and B.sub.2j,q are placed within one and the same block of greater size permuted by a transposition of the higher stage E.sub.q+1.

A volumetric data structure models a particular volume representing the particular volume at a plurality of levels of detail. A first entry in the volumetric data structure includes a first set of bits representing voxels at a first level of detail, the first level of detail includes the lowest level of detail in the volumetric data structure, values of the first set of bits indicate whether a corresponding one of the voxels is at least partially occupied by respective geometry, where the volumetric data structure further includes a number of second entries representing voxels at a second level of detail higher than the first level of detail, the voxels at the second level of detail represent subvolumes of volumes represented by voxels at the first level of detail, and the number of second entries corresponds to a number of bits in the first set of bits with values indicating that a corresponding voxel volume is occupied.

Representative apparatus, method, and system embodiments are disclosed for configurable computing. A representative system includes an asynchronous packet network; a plurality of configurable circuits arranged in an array, each configurable circuit coupled to the asynchronous packet network and adapted to perform a plurality of computations; and a dispatch interface circuit adapted to partition the plurality of configurable circuits into one or more separate partitions of configurable circuits and to load one or more computation kernels into each partition of configurable circuits. The dispatch interface circuit may load balance across the partitions of configurable circuits by starting threads for execution in the partition having the highest number of available thread identifiers. The dispatch interface may also assert a partition enable signal to merge the one or more separate partitions and assert a stop signal to all configurable circuits of the one or more separate partitions of configurable circuits.

A method includes receiving a request to modify a first value of a first field of a first item in a self-describing data system, and obtaining a domain comprising items in the self-describing data system. The first item and a second item are included in items, and the second item comprises a second field having a second value. The method includes calculating, based on a rule of the second field, a dependency of the second value on the first value. The rule specifies how the second value is to be calculated using the first value. The method includes modifying, based on the request, the first value. The method includes receiving an event triggered by the modification to the first value. The method includes, responsive to the event, calculating the second value based on the rule, and storing the second value in the second field.