A method and computer program product for performing machine learning inferences are disclosed. A set of input records to be processed by decision trees is selected, and the decision trees are run. Running the decision trees includes identifying operations to be performed as matrix elements, wherein the matrix elements correspond to the input records. Running the decision trees also includes using vector processing to process disjoint subsets of the matrix elements based on vector instructions operating on data stored in vector registers, such that the matrix elements of each subset of the disjoint subsets are processed in parallel. All leaf nodes of each decision tree involved are processed as split nodes looping to themselves until a termination condition is met. The termination condition is met if at least one of the leaf nodes has been reached for each of the decision trees involved.

Host data is written to a set of pages of a page stripe of a storage area of a memory sub-system. A set of exclusive or (XOR) parity values corresponding to the host data written to a portion of the set of pages of the storage area is generated. An additional XOR parity value is generated by executing an XOR operation using the set of XOR parity values. Parity data including the set of XOR parity values and the additional XOR parity value is stored in a cache memory of the memory sub-system. The parity data is written to an available page stripe of the storage area.

An apparatus and method are described for performing efficient Boolean operations in a pipelined processor which, in one embodiment, does not natively support three operand instructions. For example, in one embodiment, a processor comprises: a set of registers for storing packed operands; Boolean operation logic to execute a single instruction which uses three or more source operands packed in the set of registers, the Boolean operation logic to read at least three source operands and an immediate value to perform a Boolean operation on the three source operands, wherein the Boolean operation comprises: combining a bit read from each of the three operands to form an index to the immediate value, the index identifying a bit position within the immediate value; reading the bit from the identified bit position of the immediate value; and storing the bit from the identified bit position of the immediate value in a destination register.

Described herein are systems and techniques for privacy-preserving unsupervised learning. The disclosed system and methods can enable separate computers, operated by separate entities, to perform unsupervised learning jointly based on a pool of their respective data, while preserving privacy. The system improves efficiency and scalability, while preserving privacy and avoids leaking a cluster identification. The system can jointly compute a secure distance via privacy-preserving multiplication of respective data values x and y from the computers based on a 1-out-of-N oblivious transfer (OT). In various embodiments, N may be 2, 4, or some other number of shares. A first computer can express its data value x in base-N. A second computer can form an ×N matrix comprising random numbers m.sub.i,0 and the remaining elements m.sub.i,j=(yjN.sup.i-m.sub.i,0) mod . The first computer can receive an output vector from the OT, having components m.sub.i=(yx.sub.i N.sup.i-m.sub.i,0) mod .

A Reduced Instruction Set Computer (“RISC”) supporting large-word operations in a computing environment is disclosed. In one implementation, in response to receiving one or more control signals from a central processing unit (“CPU”), a set of operations are executed on a state of a special purpose execution unit (“SPU”) having a plurality of SPU registers, the SPU being associated with the CPU and the state of the SPU having word widths of one or more of the plurality of registers being greater in size than word widths of a plurality of CPU registers of a computing system and a set of state-master bits to synchronize the state of the SPU and a state of the CPU. The results of the set of operations are stored in the plurality of CPU registers or an alternative set of the plurality of SPU registers.

A calculator includes: registers each including sub-registers that hold pieces of data for use in operation; an operator that executes, in parallel, operations of the pieces of data; and a memory configured to hold a first vector and second vectors to be compared with the first vector. Each second vector is divided into sub-vectors and sub-vector groups each including the sub-vectors of the second vectors are arranged in units of sub-vector groups. A first process of transferring one of sub-vectors of the first vector to sub-registers of a first register among the registers, a second process of transferring the sub-vector group of the second vectors corresponding to the transferred sub-vector of the first vector to sub-registers of a second register, the sub-vector group being held in the memory, and a third process of calculating and integrating numbers of mismatches between bit values of the sub-vectors held are repeatedly executed.

A method for supporting architecture speculation in an out of order processor is disclosed. The method comprises fetching two threads into the processor, wherein a first thread executes in a speculative state and a second thread executes in a non-speculative state. The method also comprises enabling a speculative scope for an execution of the first thread and a non-speculative scope for an execution of the second thread in an architecture of the processor, wherein the speculative scope and the non-speculative scope can both be fetched into the architecture and be present concurrently.

A system for computing. In some embodiments, the system includes: a memory, the memory including one or more function-in-memory circuits; and a cache coherent protocol interface circuit having a first interface and a second interface. A function-in-memory circuit of the one or more function-in-memory circuits may be configured to perform an operation on operands including a first operand retrieved from the memory, to form a result. The first interface of the cache coherent protocol interface circuit may be connected to the memory, and the second interface of the cache coherent protocol interface circuit may be configured as a cache coherent protocol interface on a bus interface.

A method of encoding input data includes receiving the input data that includes a plurality of input words including a first input word and a second input word, generating a plurality of converted words including a first converted word and a second converted word, the first converted word being based at least on the first input word, the second converted word being based on the first converted word and the second input word, identifying a key value based on the plurality of converted words, and generating a plurality of coded words based on the key value and the plurality of converted words.

A method includes processing event data to detect a status of a network function. The event data is processed based on two or more conditions defined by a correlation policy. The correlation policy includes a non-deterministic finite automata tree (NFAT) structure correlation policy having a policy type and a logic-gate. The method additionally includes determining the policy type of the NFAT structure correlation policy. The method also includes determining whether a first value of the two or more conditions is indicative of whether a first condition is satisfied. The method further includes determining whether a second value of the two or more conditions is indicative of whether the second condition is satisfied. The method additionally includes determining whether the NFAT structure correlation policy is satisfied based on the first value, the second value, the logic-gate and the policy type.