Various implementations described herein relate to systems and methods for providing data protection and recovery for drive failures, including receiving, by a storage device, a write request from a host operatively coupled to a storage device, and determining, by the storage device instead of the host, an XOR result by performing an XOR operation of new data and existing data. The new data is received from the host. The existing data is stored in the non-volatile storage.

Devices and techniques for pipeline merging in a circuit are described herein. A parallel pipeline result can be obtained for a transaction index of a parallel pipeline. Here, the parallel pipeline is one of several parallel pipelines that share transaction indices. An element in a vector can be marked. The element corresponds to the transaction index. The vector is one of several vectors respectively assigned to the several parallel pipelines. Further each element in the several vectors corresponds to a possible transaction index with respective elements between vectors corresponding to the same transaction index. Elements between the several vectors that correspond to the same transaction index can be compared to determine when a transaction is complete. In response to the transaction being complete, the result can be released to an output buffer in response to the transaction being complete.

Techniques for command bus training to a memory device includes triggering a memory device to enter a first or a second command bus training mode, outputting a command/address (CA) pattern via a command bus and compressing a sampled CA pattern returned from the memory device based on whether the memory device was triggered to be in the first or the second command bus training mode.

Examples of the present disclosure provide apparatuses and methods related to performing comparison operations in a memory. An example apparatus might include a first group of memory cells coupled to a first access line and configured to store a first element. An example apparatus might also include a second group of memory cells coupled to a second access line and configured to store a second element. An example apparatus might also include sensing circuitry configured to compare the first element with the second element by performing a number of AND operations, OR operations, SHIFT operations, and INVERT operations without transferring data via an input/output (I/O) line.

An operating method of a memory device, which includes a first memory region and a second memory region, includes reading first data from the first memory region and storing the read first data in a data buffer block, performing a first XOR operation on the first data provided from the data buffer block and second data read from the second memory region to generate first result data, writing the first data stored in the data buffer block in the second memory region, performing a second XOR operation on the first data and the first result data to generate the second data, storing the generated second data in the data buffer block, and writing the second data stored in the data buffer block in the first memory region.

The invention presents a solution in which blockchain Transactions are created to implement the functionality of a logic gate. The invention may be implemented on the Bitcoin platform or an alternative blockchain platform. The transaction includes a locking script which comprises instructions selected so as to implement the functionality of a logic gate such as OR, AND, XOR, NOT and so on. In some examples, the instructions may be provided in a hashed form. When the script is executed (because a second transaction is attempting to spend the output associated with the locking script) the inputs will be processed by the conditional instructions to provide an output of TRUE or FALSE. The second transaction is transmitted to the blockchain network for validation and, if determined to be valid, it will be written to the blockchain. Validation of the second transaction can be interpreted as a TRUE output. Thus, the locking script of the first transaction provides the functionality of the desired logic gate. The invention provides numerous advantages and can be used in a wide variety of applications, such as for the implementation of control systems and processes.

An encryption specification named “MetaEncrypt” implemented as a method and associated apparatus is disclosed for unbreakable encryption of data, code, applications, and other information that uses a symmetric key for encryption/decryption and to configure the underlying encryption algorithms being utilized to increase the difficulty of mathematically modeling the algorithms without possession of the key. Data from the key is utilized to select several encryption algorithms utilized by MetaEncrypt and configure the algorithms during the encryption process in which block sizes are varied and the encryption technique that is applied is varied for each block. Rather than utilizing a fixed key of predetermined length, the key in MetaEncrypt can be any length so both the key length and key content are unknown. MetaEncrypt's utilization of key data makes it impossible to model its encryption methodology to thereby frustrate cryptographic cracking and force would be hackers to utilize brute force methods to try to guess or otherwise determine the key.

Systems, apparatuses, and methods related to bit string operations using a computing tile are described. An example apparatus includes computing device (or “tile”) that includes a processing unit and a memory resource configured as a cache for the processing unit. A data structure can be coupled to the computing device. The data structure can be configured to receive a bit string that represents a result of an arithmetic operation, a logical operation, or both and store the bit string that represents the result of the arithmetic operation, the logical operation, or both. The bit string can be formatted in a format different than a floating-point format.

An article of manufacture includes a non-transitory machine-readable medium. The medium includes instructions that cause a processor to execute a shift instruction. The shift instruction is to cause a source data in memory to be shifted left or shifted right. The shift instruction is to include a source parameter and a bit size parameter. The processor is to execute the shift instruction through a shift of a first source word of the source data by the bit size parameter to yield a first intermediate word, a shift of a second source word of the source data by the bit size parameter to yield a second intermediate word and a first set of shifted-out bits, and through execution of a logical OR operation on the first intermediate word and the first set of shifted-out bits to yield a first result word.

An information processing apparatus sets, in a second program: a second array where an occurrence pattern indicating whether elements are subjected to computation is a repetition of a pattern for every power-of-two number of elements; a second mask array generated by adding masks indicating that corresponding elements are not subjected to the computation to a first mask array so that the second mask array includes as many masks as the number of elements included in a second pattern; and a second instruction string providing an instruction for the computation of elements corresponding to masks indicating that corresponding elements are subjected to the computation, among the elements set in the second array. Each mask in the second mask array to be applied to an element in the second array is specified by a bitwise logical AND using a value indicating the position of the element in the second array.