A system includes an ARM core processor, a programmable regulator, a compiler, and a control unit, where the compiler uses a performance association outcome to generate a 2-bit regulator control values encoded into each individual instruction. The system can provide associative low power operation where instructions govern the operation of on-chip regulators or clock generator in real time. Based on explicit association between long delay instruction patterns and hardware performance, an instruction based power management scheme with energy models are formulated for deriving the energy efficiency of the associative operation. An integrated voltage regulator or clock generator is dynamically controlled based on instructions existing in the current pipeline stages leading to additional power saving. A compiler optimization strategy can further improve the energy efficiency.

In an embodiment, a processor for demotion includes a plurality of cores to execute instructions and a demotion control circuit. The demotion control circuit is to: for each core of the plurality of cores, determine an average count of power state break events in the core; determine a sum of the average counts of the plurality of cores; determine whether the average count of a first core exceeds a first demotion threshold; determine whether the sum of the average counts of the plurality of cores exceeds a second demotion threshold; and in response to a determination that the average count of the first core exceeds the first demotion threshold and the sum of the average counts exceeds the second demotion threshold, perform a power state demotion of the first core. Other embodiments are described and claimed.

An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to manage a persistent storage media, provide a host with an indication of a time for the host to initiate a subsequent wake-up for data management of the persistent storage media, and perform data management of the persistent storage media in response to a host-initiated wake-up from a zero power state. Other embodiments are disclosed and claimed.

The present disclosure provides a computation device and method, which are capable of using a single instruction to complete a transpose computation of a matrix of any size within constant time. Compared with conventional methods for performing a matrix transpose computation, the device and method may reduce the time complexity of a matrix transpose computation as well as making the usage of the computation simpler and more efficient.

A Guest Operating System wake-up method, device, electronic apparatus, and a computer readable medium, which are applicable to an intelligent terminal, the intelligent terminal includes a Host Operating System and at least one Guest Operating System is provided. The method includes: determining an operating mode of the Guest Operating System after obtaining network data having the Guest Operating System as its destination address, wherein the operating mode is a suspended mode or an active mode; generating a wake-up request when the operating mode of the Guest Operating System is the suspended mode; and enabling the Guest Operating System to enter into the active mode according to the wake-up request so as to respond to the network data. The Guest Operating System enables accurate and efficient responses to network data transmission in the multi-system environment, thereby reducing reduce resource consumption and enhance user experience.

A method for synchronizing startup of a plurality of power supplies in an electrical system includes supplying input power to a first power supply to supply power to an auxiliary converter and an auxiliary controller. The method also includes monitoring, via the auxiliary controller, a signal shared by each of the plurality of power supplies. The method further includes incrementally increasing, via the auxiliary controller, a value of the shared signal to a next incremental value of a plurality of specified values. The method also includes enabling, via the auxiliary controller, each of the power supplies to supply power to a load when the value of the shared signal is set to a maximum value of the specified values.

An arithmetic processing device includes a plurality of arithmetic processing units each including, an internal circuit that, in an instruction processing state in which an instruction is processed, processes the instruction and that, in an instruction processing stopped state in which instruction processing is stopped, transitions to a state of power save operation, and a power control circuit that disables the power save operation; and a monitoring circuit that monitors the instruction processing stopped state of the plurality of arithmetic processing units and counts the number of the arithmetic processing units in the instruction processing stopped state. The power control circuit of each of the plurality of arithmetic processing units disables the power save operation of the arithmetic processing unit in the instruction processing stopped state, in a case where the number of the arithmetic processing units in the instruction processing stopped state exceeds a threshold.

Embodiments relate to improving user experiences when executing binary code that has been translated from other binary code. Binary code (instructions) for a source instruction set architecture (ISA) cannot natively execute on a processor that implements a target ISA. The instructions in the source ISA are binary-translated to instructions in the target ISA and are executed on the processor. The overhead of performing binary translation and/or the overhead of executing binary-translated code are compensated for by increasing the speed at which the translated code is executed, relative to non-translated code. Translated code may be executed on hardware that has one or more power-performance parameters of the processor set to increase the performance of the processor with respect to the translated code. The increase in power-performance for translated code may be proportional to the degree of translation overhead.

Techniques are described for managing the optimized refreshing of metadata associated with online and live systems. In some implementations, a set of metadata modules associated with one or more entities are identified, the metadata modules defining metadata associated with a particular data model for the associated entities. A request to initiate a refreshing of the metadata for a subset of the set of metadata modules is identified. Each metadata module from the subset of the set of metadata modules is prioritized into a prioritization order. A determination is made as to whether two or more idle database connections are available. In response to determining that two or more idle database connections are available, a concurrent refresh of the subset of the set of metadata modules is initialized in the prioritization order.

A computer processor includes a branch prediction unit that includes a local branch predictor and a global branch predictor. Managing power consumption in such a computer processor includes, for each of a plurality of branch instructions: performing, by the local branch predictor, a local branch prediction; performing, by each of the global branch predictors, a global branch prediction; determining to utilize the local branch prediction over the global branch predictions as a branch prediction for the branch instruction; incrementing a value of a counter; determining whether the value of the counter exceeds a predetermined threshold; and if the value of the counter exceeds the predetermined threshold, powering down at least one of the global branch predictors and configuring the branch prediction unit to bypass the powered down global branch predictor for branch predictions of subsequent branch instructions.