Preventing the observation of the side effects of mispredicted speculative execution flows using restricted speculation. In an embodiment a microprocessor comprises a register file including a plurality of entries, each entry comprising a value and a flag. The microprocessor (i) sets the flag corresponding to any entry whose value results from a memory load operation that has not yet been retired or cancelled, or results from a calculation that was derived from a register file entry whose corresponding flag was set, and (ii) clears the flag corresponding to any entry when the operation that generated the entry's value is retired. The microprocessor also comprises a memory unit that is configured to hold any memory load operation that uses an address whose value is calculated based on a register file entry whose flag is set, unless all previous instructions have been retired or cancelled.

Detailed herein are systems, apparatuses, and methods for a computer architecture with instruction set support to mitigate against page fault- and/or cache-based side-channel attacks. In an embodiment, an apparatus includes a decoder to decode a first instruction, the first instruction having a first field for a first opcode that indicates that execution circuitry is to set a first flag in a first register that indicates a mode of operation that redirects program flow to an exception handler upon the occurrence of an event. The apparatus further includes execution circuitry to execute the decoded first instruction to set the first flag in the first register that indicates the mode of operation and to store an address of an exception handler in a second register.

A data processing apparatus is provided that comprises fetch circuitry to fetch an instruction stream comprising a plurality of instructions, including a status updating instruction, from storage circuitry. Status storage circuitry stores a status value. Execution circuitry executes the instructions, wherein at least some of the instructions are executed in an order other than in the instruction stream. For the status updating instruction, the execution circuitry is adapted to update the status value based on execution of the status updating instruction. Flush circuitry flushes, when the status storage circuitry is updated, flushed instructions that appear after the status updating instruction in the instruction stream.

An information handling system (IHS) includes a battery management unit (BMU) and an embedded controller (EC). The EC is operable for detecting a trigger for monitoring power consumption in light of a first condition, capturing a state of the IHS, writing data representing the state to a power profile log, annotating the log with an identifier of a point at which logging associated with the first condition begins, obtaining, from the BMU, power data representing an amount of current flowing from or charge delivered by a battery, writing at least some power data to the log, detecting a trigger for ending monitoring associated with the first condition, annotating the log with an identifier of a point at which logging associated with the first condition ends, and generating, dependent on the annotations of the identifiers in the log, a power profile report indicating power consumption associated with the first condition.

Detailed herein are systems, apparatuses, and methods for a computer architecture with instruction set support to mitigate against page fault and/or cache-based side-channel attacks. In an embodiment, a processor includes a decoder to decode an instruction into a decoded instruction, the instruction comprising a first field that indicates an instruction pointer to a user-level event handler; and an execution unit to execute the decoded instruction to, after a swap of an instruction pointer that indicates where an event occurred from a current instruction pointer register into a user-level event handler pointer register, push the instruction pointer that indicates where the event occurred onto call stack storage, and change a current instruction pointer in the current instruction pointer register to the instruction pointer to the user-level event handler.

Processing circuitry (85) supports a vector atomic memory update instruction identifying an address vector, for triggering at least one atomic memory update operation for performing an atomic memory update to a memory location having an address determined based on a corresponding active data element of the address vector. When a fault condition is determined for the address determined using a given faulting active data element of the address vector, atomic memory update operations for that element and any subsequent element in a predetermined sequence are suppressed. If the faulting element is the first active data element in the sequence, a fault handling response is triggered, while otherwise the fault handling response is suppressed and status information is stored indicating which element is the faulting element.

In one embodiment, a method includes accessing a loaded but paused source process executable and disassembling the source process executable to identify a system call to be instrumented and an adjacent relocatable instruction. Instrumenting the system call includes building a trampoline for the system call that includes a check flag instruction at or near an entry point to the trampoline and two areas of the trampoline that are selectively executed according to results of the check flag instruction. Building a first area of the trampoline includes providing instructions to execute a relocated copy of the adjacent relocatable instruction and return flow to an address immediately following the adjacent relocatable instruction. Building a second area of the trampoline includes providing instructions to invoke at least one handler associated with executing a relocated copy of the system call and return flow to an address immediately following the system call.

A method of controlling a data processor to perform data processing operations is disclosed in which a host processor prepares one or more queue(s) of operations for execution by the data processor. When an error is encountered in the processing of an operation for one of the one or more queue(s), a queue can be set into an error state in which instructions that may have a data dependency on another operation are not executed. The host processor includes in the queues error barrier instructions that divide the respective queues into sets of operations between which there are no data processing dependencies. An error state for a queue can thus be cleared when its processing reaches the next error barrier instruction in the queue.

An arithmetic circuit performs a floating-point operation. A floating-point register includes entries each allocated to an architectural register or a renaming register. An operation execution controller circuit issues a floating-point operation instruction and outputs a termination report of the floating-point operation before the floating-point operation is terminated. When exception handling is not performed at the time of instruction completion even when an exception is detected in the operation of the floating-point operation instruction, an instruction completion controller circuit outputs a release instruction that indicates a release of a renaming register when instruction execution is completed after the termination report is received. An instruction decoder circuit receives the release instruction, allocates a first entry allocated to an architectural register that stores an execution result of the floating-point operation to a renaming register, and allocates a second entry allocated to a renaming register in the floating-point operation to the architectural register.

Systems and methods are disclosed for executing instructions with a block-based processor. Instructions can be executed in any order as their dependencies arrive, but the individual instructions are committed in a serial fashion. Further, exception handling can be performed by storing transient state for an instruction block and resuming by restoring the transient state. This allows programmers to see intermediate state for the instruction block before the subject block has committed. In one examples of the disclosed technology, a method of operating a processor executing a block-based instruction set architecture includes executing at least one instruction encoded for an instruction block, responsive to determining that an individual instruction of the instruction block can commit, advancing a commit frontier for the instruction block to include all instructions in the instruction block that can commit, and committing one or more instructions inside the advanced commit frontier.