In some examples, executable code causes a processor to execute a first function and enter a system management mode responsive to receipt of a first system management interrupt during the execution of the first function. The executable code causes the processor to pause execution of the first function, save a state of the processor in the system management mode, and exit the system management mode. The executable code causes the processor to execute a second function identified by the first system management interrupt and receive a second system management interrupt to enter the system management mode. The executable code causes the processor to restore the state of the processor in the system management mode and exit the system management mode. The executable code causes the processor to resume execution of the first function after exiting the system management mode.

A system management mode (SMM) runtime resiliency manager (SRM) augments computing resource protection policies provided by an SMM policy shim The SMM shim protects system resources by deprivileging system management interrupt (SMI) handlers to a lower level of privilege (e.g., ring 3 privilege) and by configuring page tables and register bitmaps (e.g., I/O, MSR, and Save State register bitmaps). SRM capabilities include protecting the SMM shim, updating the SMM shim, protecting a computing system during SMM shim update, detecting SMM attacks, and recovering attacked or faulty SMM components.

A processor with reduced interrupt latency is disclosed. An apparatus includes a processor core and a cache subsystem having a cache controller and a cache. The processor core is configured to submit, to the cache controller, requests for access to the cache, wherein a given request for access to the cache specifies whether the given request is abandonable or non-abandonable in an event of an interrupt request. In response to a particular interrupt request, the processor core may provide an indication to cause the cache controller to abandon requests for access to the cache identified as abandonable. After receiving an acknowledgement from the cache controller that the abandonable requests have been abandoned, the processor core may begin execution of an interrupt handler in order to service the interrupt request.

In a system including a primary process followed by a secondary process, which are performed serially and sequentially, i.e., in a FIFO manner, where the secondary process is downstream of the primary process, the disclosed embodiments relate to selective/conditional secondary processing of electronic data transaction request messages, which speeds up the primary processing of the electronic data transaction request messages, reduces the amount of computing resources wasted on calculating inaccurate information, and reduces the usage of network resources associated with publishing market data feeds and receiving new responsive messages.

In an embodiment, an electronic circuit includes: a plurality of signal channels; a signal collection circuit configured to determine an action of the electronic circuit based on channel signals from the plurality of signal channels; and a first signal management circuit coupled between the plurality of signal channels and the signal collection circuit, the first signal management circuit including: a set of internal registers, a set of user registers, and a decoder configured to program the set of internal registers based on a content of the set of user registers, where the first signal management circuit is configured to receive the channel signals via the plurality of signal channels, generate first aggregated signals based on the received channel signals and a content of the set of internal registers, and transmitting the first aggregated signals to the signal collection circuit.

Embodiments of the present disclosure relate to systems and methods for installing a program within a CICS region without an antecedent program. A CICS region where the program is to be installed may detect an initiating event, the CICS region executing logical units of work that each correspond to a task of a host operating system (OS). The initiating event may generate a first logical unit of work to intercept service calls made by the CICS region. In response to the first logical unit of work intercepting a first service call, control of execution of the first service call may be transitioned from the host OS to a CICS execution API. The CICS execution API may issue one or more API calls related to installation of the program, wherein the CICS execution API executes the one or more API calls as if they are part of the first service call.

Embodiments of this application relate to the field of communications technologies, and provide a system service timeout processing method and an apparatus. The method includes: when a target system service thread in at least one system service thread times out, determining, by a terminal, a first application process communicating with the target system service thread, where the timeout of the target system service thread includes at least one of the following: a locked object occupied by the target system service thread is not released within a preset time, and the target system service thread is blocked; and ending, by the terminal, the first application process.

Instruction processing is performed for an instruction. The instruction is configured to perform a plurality of functions, in which a function of the plurality of functions is to be performed in a plurality of processing phases. A processing phase is defined to store up to a select amount of data. The select amount of data is based on the function to be performed. At least one function of the plurality of functions has a different value for the select amount of data than at least one other function. A determination is made as to whether a store into a designated area occurred based on processing a select processing phase of a select function. Based on determining that the store into the designated area occurred, an interrupt is presented, and based on determining that the store into the designated area did not occur, instruction processing is continued.

A storage device includes a nonvolatile memory device and a storage controller. The storage controller accesses the nonvolatile memory device based on a request of an external host device. The storage controller sends a signal to the external host device, based a throughput of accessing the nonvolatile memory device being within a specific range.

A data processing device is described including one or more processors implementing a plurality of data processing entities, one or more software interrupt nodes and an access register for each software interrupt node. The access register specifies which one or more data processing entities of the plurality of data processing entities is/are each allowed to, as interrupt source data processing entity, trigger an interrupt service request on the software interrupt node for another one of the plurality of data processing entities as an interrupt target processing entity. Each software interrupt node is configured to forward an interrupt service request triggered by an interrupt source data processing entity which is allowed to trigger an interrupt service request on the software interrupt node to an interrupt target processing entity.