A transaction management system includes a storage circuit and a processing circuit. The storage circuit stores a current tag value of a tag ID of a device and a tag value associated with a transaction initiated by the device. The processing circuit receives a reset query to determine an availability of the device for reset. When the device is to be reset, the current tag value of the tag ID is updated. Further, the processing circuit generates an acknowledgment in response to the reset query such that the device is reset based on the acknowledgment. The updated tag ID ensures that responses for transactions that are initiated by the device before the reset are discarded.

In one embodiment of the present invention, a streaming multiprocessor (SM) uses a tree of nodes to manage threads. Each node specifies a set of active threads and a program counter. Upon encountering a conditional instruction that causes an execution path to diverge, the SM creates child nodes corresponding to each of the divergent execution paths. Based on the conditional instruction, the SM assigns each active thread included in the parent node to at most one child node, and the SM temporarily discontinues executing instructions specified by the parent node. Instead, the SM concurrently executes instructions specified by the child nodes. After all the divergent paths reconverge to the parent path, the SM resumes executing instructions specified by the parent node. Advantageously, the disclosed techniques enable the SM to execute divergent paths in parallel, thereby reducing undesirable program behavior associated with conventional techniques that serialize divergent paths across thread groups.

In a computer supporting Transactional Memory (TM) Transaction Execution (TX), use of speculative branch prediction is programmably suspended during TX, and programmably resumed. The branch prediction suspension may cause the execution of one or more instructions following the branch instruction to stall in the pipeline until branch conditions and branch target addresses are resolved.

A method for thread-safe development of a computer program configured for parallel thread execution comprises maintaining a digital record of read or write access to a data object from each of a plurality of sibling threads executing on a computer system. Pursuant to each instance of read or write access from a given sibling thread, an entry comprising an indicator of the access type is added to the digital record. The method further comprises assessing the thread safety of the read or write access corresponding to each entry in the digital record and identifying one or more thread-unsafe instances of read or write access based on the assessment of thread safety.

A method for operating a multi-transaction memory system, the method includes: storing Logical Block Address (LBA) information changed in response to a request from a host and a transaction identification (ID) of the request into one page of a memory block; and performing a transaction commit in response to a transaction commit request including the transaction ID from the host, wherein the performing of the transaction commit includes: changing a valid block bitmap in a controller of the multi-transaction memory system based on the LBA information.

A system for executing a data flow graph comprises: at least two first actors each comprising means for independently executing a computation of a same data set comprising at least one datum, and producing a quality descriptor of the data set, the execution of the computation by each of at least two first actors being triggered by a synchronization system; a third actor, comprising means for triggering the execution of the computation by each of at least two first actors, and initializing a clock configured to emit an interrupt signal when a duration has elapsed; a fourth actor, comprising means for executing, at the latest at the interrupt signal from the clock: the selection, from the set of at least two first actors having produced a quality descriptor, of the one whose descriptor exhibits the most favorable value; the transfer of the data set computed by the selected actor.

A method and apparatus for registering a user-handler in hardware for transactional memory is herein described. A user-accessible register is to hold a reference to a transactional handler. An event register may also be provided to specify handler events, which may be done utilizing user-level software, privileged software, or by hardware. When an event is detected execution vectors to the transaction handler based on the reference to the transactional handler held in the user-accessible register. The transactional handler handles the event and then execution returns to normal flow.

An apparatus (2) has processing circuitry (6) having access to a first processing resource (20-0) and a second processing resource (20-3). A first thread can be processed using the first processing resource. In a thread mode the second processing resource (20-3) can be used to process a second thread while in a transaction mode the second processing resource (20-3) can be used to process a transaction of the first thread comprising a number of speculatively performed operations for which results are committed at the end of the transaction. By sharing resources for supporting additional threads and supporting transactions, circuit area and power consumption can be reduced.

Approaches for more efficiently executing calls to native code from within a managed execution environment are described. The techniques involve attempting to execute a native call, such as a call to a C function from within Java code, using a single hardware transaction. Not only is the native code executed in a hardware transaction, but also various transitional operations needed for transitioning between managed execution mode and native execution mode. If the hardware transaction is successful, at least some of the operations that would normally be performed during transitions between modes may be omitted or simplified. If the hardware transaction is unsuccessful, the native calls may be performed as they normally would, outside of hardware transactions.

An example system for speculative execution event counter checkpointing and restoring may include a plurality of symmetric cores, at least one of the symmetric cores to simultaneously process a plurality of threads and to perform out-of-order instruction processing for the plurality of threads; at least one shared cache circuit to be shared among two or more the of symmetric cores. The system may further include a memory controller to couple the symmetric cores to a system memory and a data communication interface to couple one or more of the cores to input/output devices. The system may further include event counter circuitry comprising: a plurality of event counters including programmable event counters and fixed event counters and one or more configuration registers to store configuration data to specify an event type to be counted by the programmable event counters, wherein at least one of the one or more configuration registers is to store configuration data for a plurality of the programmable event counters. The system may further include transactional memory circuitry to process transactional memory operations including load operations and store operations, the transactional memory circuitry to process a transaction begin instruction to indicate a start of a transactional execution region of a program, a transaction end instruction to indicate an end of the transactional execution region, and a transaction abort instruction to abort processing of the transactional execution region. The system may further include transaction checkpoint circuitry to store a processor state at the start of the transactional execution region of the program, the processor state including values of one or more of the event counters. The system may further include lock elision circuitry to cause critical sections of the program to execute as transactions on multiple threads without acquiring a lock, the lock elision circuitry to cause the critical sections to be re-executed non-speculatively using one or more locks in response to detecting a transaction failure.