Patent classifications
G06F9/528
Speculative hint-triggered activation of pages in memory
Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. In various embodiments, a computing system includes a computing resource and a memory controller coupled to a memory device. The computing resource selectively generates a hint that includes a target address of a memory request generated by the processor. The hint is sent outside the primary communication fabric to the memory controller. The hint conditionally triggers a data access in the memory device. When no page in a bank targeted by the hint is open, the memory controller processes the hint by opening a target page of the hint without retrieving data. The memory controller drops the hint if there are other pending requests that target the same page or the target page is already open.
System and method for implementing reader-writer locks using hardware transactional memory
Transactional reader-writer locks may leverage available hardware transactional memory (HTM) to simplify the procedures of the reader-writer lock algorithm and to eliminate a requirement for type stable memory An HTM-based reader-writer lock may include an ordered list of client-provided nodes, each of which represents a thread that holds (or desires to acquire) the lock, and a tail pointer. The locking and unlocking procedures invoked by readers and writers may access the tail pointer or particular ones of the nodes in the list using various combinations of transactions and non-transactional accesses to insert nodes into the list or to remove nodes from the list. A reader or writer that owns a node at the head of the list (or a reader whose node is preceded in the list only by other readers' nodes) may access a critical section of code or shared resource.
RESOURCE PROCESSING METHOD AND DEVICE
A resource processing method and device, the method comprising: establishing, according to a first resource storage for storing a target resource, a corresponding second resource storage, the second resource storage comprising resource record information of the target resource; according to a resource display mode corresponding to the first resource storage, displaying the resource record information of the target resource; if the target resource is received by the first resource storage, updating the first resource storage according to the second resource storage. The method establishes a second resource storage corresponding to a first resource storage, and obtains and displays resource record information of a target resource, thus reasonably arranging a resource allocation flow path according to a resource acquisition condition, supporting the advance allocation of resource in transit and shortening resource vacancy time, and increasing resource allocation efficiency and resource utilization rate.
EFFICIENT AND THREAD-SAFE OBJECTS FOR DYNAMICALLY-TYPED LANGUAGES
A method may include creating objects by executing a program in a first thread. Creating the objects may include allocating, for each object, storage based on a shape assigned to the object. The storage may include separate, non-reusable storage locations. Each storage location may correspond to a field of the object. The shape may include a sharing status and a mapping of each field of the object to a storage location. The method may further include detecting that the program is initiating a second concurrent thread of execution, and designating a subset of objects as shared objects. Designating the subset of objects as shared objects may include setting the sharing status of the shape assigned to each shared object to indicate that the object is shared. The method may further include initiating tracking of shared objects and implementing a write barrier when writing to shared objects.
SPECULATIVE EXECUTION OF A STREAM OF CHANGES
Example implementations relate to speculative execution of a stream of changes. For example, a computing device may include at least one processor. The at least one processor may receive a stream of changes concurrently received by an online transaction processing (OLTP) database engine in communication with the computing device. The at least one processor may process the stream of changes based on speculative execution and verify that an order of the stream of changes processed based on speculative execution matches an OLTP order of the stream of changes committed by the OLTP database engine. The at least one processor may send the stream of changes processed based on speculative execution to an online analytical processing (OLAP) database engine to be stored in an OLAP database.
Hybrid tracking of transaction read and write sets
Embodiments of the invention relate to tracking processor transactional read and write sets, thereby eliminating speculative mispredictions. Both non-speculative read set and write set indications are maintained for a transaction. The indications are stored in cache. In addition, load and write queues of addresses are maintained. The load queue of addresses relates to speculative members of a read set and the write queue of addresses relates to speculating member of a write set. For a received read request, a transaction resolution process takes place, and a resolution is performed if an address match in the write queue is detected. Similarly, for a receive write request the transaction interference additionally checks the load queue and the non-speculative read set for the pending address.
Partial order procedure planning device, partial order procedure planning method and partial order procedure planning program
A partial order procedure planning device 10 is provided with: a first generation unit 11 which generates a first condition of a removable order relationship under a predetermined restriction among order relationships between operations in a serial procedure in which a plurality of operations, which transit the state of a state element from an initial state to a target state, are arranged in series; a second generation unit 12 which generates a second condition of an order relationship, which is required to satisfy a transient requirement that is required to satisfy the state element while a state among the order relationships is transitioned from the initial state to the target state; and a determination unit 13 which determines, as the order relationship to be deleted from the serial procedure, an order relationship which satisfies the generated first condition, but does not satisfy the generated second condition.
System and method of providing correction assistance on machine learning workflow predictions
A system and method of for providing assistance to complete machine learning on workflow engines that deal with machine learning flows comprising operators configured in a coordinate grid. The process analyzes the positions and composition of operators, branches, inconsistencies, collisions and redundancy in the workflow in order to suggest to the user which changes should be made to the workflow.
Checking lock variables for transactions in a system with transactional memory support
In an apparatus (2) with transactional memory support, a predetermined type of transaction start instruction or a subsequent instruction following the predetermined type of transaction start instruction triggers capture of a lock identifier which identifies a lock variable for controlling exclusive access to at least one resource. In response to a predetermined type of transaction end instruction which follows the predetermined type of transaction start instruction, the lock variable is checked and commitment of results of speculatively executed instructions of the transaction is prevented or deferred when the lock variable indicates that another thread holds the exclusive access to the target resource. This approach can improve performance when executing transactions in a transactional memory based system.
System and method for dynamic enforcement of store atomicity
A computer system for dynamic enforcement of store atomicity includes multiple processor cores, local cache memory for each processor core, a shared memory, a separate store buffer for each processor core for executed stores that are not yet performed and a coherence mechanism. A first processor core load on a first processor core receives a value at a first time from a first processor core store in the store buffer and prevents any other first processor core load younger than the first processor core load in program order from committing until a second time when the first processor core store is performed. Between the first time and the second time any load younger in program load than the first processor core load and having an address matched by coherence invalidation or an address matched by an eviction is squashed.