Methods, systems, and devices for maintenance command interfaces for a memory system are described. A host system and a memory system may be configured according to a shared protocol that supports enhanced management of maintenance operations between the host system and memory system, such as maintenance operations to resolve error conditions at a physical address of a memory system. In some examples, a memory system may initiate maintenance operations based on detections performed at the memory system, and the memory system may provide a maintenance indication for the host system. In some examples, a host system may initiate maintenance operations based on detections performed at the host system. In various examples, the described maintenance signaling may include capability signaling between the host system and memory system, status indications between the host system and memory system, and other maintenance management techniques.

A verifying method for an error checking and correcting (ECC) circuit of a static random-access memory (SRAM) is provided. The SRAM comprises a storage unit, an ECC circuit and a checking circuit. The ECC circuit receives an original data and an output first data. The checking circuit obtains a second data according to an error-injecting mask. The checking circuit performs a bit operation on the first data and the second data to obtain a third data. The checking circuit writes the third data into a test target area of the storage unit and the written data as a fourth data. The checking circuit reads the fourth data from the test target area. The ECC circuit obtains a fifth data and an error message according to the fourth data. The checking circuit obtains the bit error detection result according to the error message and the second data.

An integrated memory assembly comprises a memory die and a control die bonded to the memory die. The memory die includes a memory structure of non-volatile memory cells. The control die is configured to program user data to and read user data from the memory die in response to commands from a memory controller. To utilize space more efficiently on the memory die, the control die compacts fragmented data on the memory die.

A semiconductor system includes a process control circuit configured to determine whether to perform a patrol training operation, generate a voltage code signal for adjusting a level of a reference voltage which determines a logic level of data in a target memory circuit, and adjust the voltage code signal on the basis of a fail information signal corresponding to the target memory circuit, an operation control circuit configured to receive a command and an address from a host, generate, from the command, a write signal and a read signal for performing a normal operation, and generate, from the address, an internal address for performing the normal operation and an error detection circuit configured to detect an error in the data by receiving the data from the target memory circuit, and generate the fail information signal depending on whether the error has occurred in the data.

A system includes a memory device storing groups of managed units and a processing device operatively coupled to the memory device. The processing device is to, during power on of the memory device, perform including: causing a read operation to be performed at a subset of a group of managed units; determining a bit error rate related to data read from the subset of the group of managed units; and in response to the bit error rate satisfying a threshold criterion, causing a rewrite of the data stored at the group of managed units.

A storage system comprises a non-volatile memory configured to store boot code and a control circuit connected to the non-volatile memory. In response to a first request from a host to transmit the boot code, the storage system commences transmission of the boot code to the host at a first transmission speed. Before successfully completing the transmission of the boot code to the host at the first transmission speed, it is determined the boot code transmission has failed. Therefore, the host will issue a second request for the boot code. In response to the second request for the boot code, and recognizing that this is a fallback condition because the previous transmission of the boot code failed, the storage apparatus re-transmits the boot code to the host at a lower transmission speed than the first transmission speed.

A solid state drive (SSD) includes a first storage region classified as byte addressable NV storage region and a controller communicatively coupled to the first storage region by a bus. The controller detects a reduced storage capacity of the first storage region, and in response to the detection, reclassifies the first storage region as a block addressable NV storage region. The SSD dynamically changes byte addressable NV storage regions to block addressable NV storage regions as the byte addressable NV storage regions are degraded, thereby extending the longevity of the SSD.

Embodiments combine error correction code (ECC) and transparent memory built-in self-test (TMBIST) for memory fault detection and correction. An ECC encoder receives input data and provides ECC data for data words stored in memory. Input XOR circuits receive the input data and output XOR'ed data as payload data for the data words. Output XOR circuits receive the payload data and output XOR'ed data. An ECC decoder receives the ECC data and the XOR'ed output data and generates error messages. Either test data from a controller running a TMBIST process or application data from a processor executing an application is selected as the input data. Either test address/control signals from the controller or application address/control signals from the processor are selected for memory access. During active operation of the application, memory access is provided to the processor and the controller, and the memory is tested during the active operation.

A method and apparatus for calibrating read threshold for cells of a target wordline (WL) that may be conducted on a die, in a controller connected to a memory die, or both. Voltage values of one or more adjacent WL cells are read, and based on the voltage values of the adjacent cells, cells of the target WL are grouped. A read threshold calibration is carried out on each group. The calibration thresholds are then used for read operations on the cells of each distinct group of the target WL.

Systems and methods are disclosed for checker cores for fault tolerant processing. For example, an integrated circuit (e.g., a processor) for executing instructions includes a processor core configured to execute instructions of an instruction set; an outer memory system configured to store instructions and data; and a checker core configured to receive committed instruction packets from the processor core and check the committed instruction packets for errors, wherein the checker core is configured to utilize a memory pathway of the processor core to access the outer memory system by receiving instructions and data read from the outer memory system as portions of committed instruction packets from the processor core. For example, data flow from the processor core to the checker core may be limited to committed instruction packets received via dedicated a wire bundle.