A wearable medical monitoring device includes a plurality of ECG electrodes configured to receive an ECG signal when the wearable medical monitoring device is worn by a patient, and a monitor coupled to the plurality of ECG electrodes. The monitor is configured to detect an impending cardiac event based on the received ECG signal of the patient. The device includes at least one processor configured to execute a plurality of instructions to implement an update manager configured to receive a software update corresponding to the at least one software module for the monitor, determine an event estimation of risk score for a predetermined period of time, cause an installation of the update when the event estimation of risk score indicates a low likelihood of an impending cardiac event, and cause a delay in the installation when the event estimation of risk score indicates a high likelihood of impending cardiac event.

Disclosed herein are systems and method for selectively restoring a computer system to an operational state. In an exemplary aspect, the method may create a backup image of the computer system comprising a set of data blocks, and create and start a virtual machine based on the backup image. The method may identify a subset of the data blocks accessed from the backup image during startup of the virtual machine. In response to determining that the computer system should be restored, the method may restore the subset of the data blocks such that the computer system is operational during startup, and restore a remaining set of the data blocks from the backup image after the startup of the computer system.

An information processing apparatus includes a storage unit configured to store at least a first boot program and a second boot program corresponding to the first boot program, a controller configured to read and execute a program, detect, in accordance with occurrence of a read error at reading of the first boot program, an address of a storage area storing a program in which the read error has occurred in the first boot program, and specify, from an address of a storage area storing the second boot program, an address corresponding to the detected address. The controller reads and executes the second boot program stored in the specified address.

An early boot debug system includes a first memory subsystem that includes boot instructions and a processing system that is coupled to the first memory subsystem. The processing system includes a primary processing subsystem, and a secondary processing subsystem that is coupled to the primary processing subsystem and a second memory subsystem. The secondary processing subsystem copies the boot instructions from the first memory subsystem to the second memory subsystem and executes the boot instructions from the second memory subsystem during a boot operation. The secondary processing subsystem then detects a first event during the execution of the boot instructions and, in response, generates a first event information. The secondary processing subsystem stores the first event information in the second memory subsystem to be retrieved on-demand by an administrator.

Methods, systems, and devices for host-configurable error protection are described. A host system may receive an indication of a set of logical addresses supported by the memory system and available for use by the host system. The host system may divide the set of logical addresses into subsets of logical addresses. Each subset of logical addresses may be associated with a different type of data. The host system may determine an error protection configuration for a subset of logical addresses based at least in part on the type of data associated with the subset of logical addresses. The host system may then send to the memory system an indication of the subset of logical addresses and an indication of the error protection configuration for the subset of logical addresses.

A method provides the capability to maintain integrity of a data image stored by computing a hash value (“digest”) of the data image and comparing the hash value computed for the data image with a hash value computed for the data image and kept in a non-volatile area of memory. Bit flips in the data image that are a result of memory hardware errors reveal themselves as differences in the digest computed for the data image and the computed digest for the data.

An information handling system may include a processor and a non-transitory computer-readable medium having stored thereon a program of instructions executable by the processor, the program of instructions configured to, when read and executed by the processor, receive a write request to a non-volatile memory, combine write request data and data patterns associated with the write request into a versioned log and store the versioned log in a persistent memory, and store in the persistent memory patterned-matched bits for single- and multi-bit error recovery code-based recovery.

Disclosed are techniques for managing context information for data stored within a computing device. According to some embodiments, the method can include the steps of (1) loading, into a volatile memory of the computing device, the context information from a non-volatile memory of the computing device, where the context information is separated into a plurality of portions, and each portion of the plurality of portions is separated into a plurality of sub-portions, (2) writing transactions into a log stored within the non-volatile memory, and (3) each time a condition is satisfied: identifying a next sub-portion to be processed, where the next sub-portion is included in the plurality of sub-portions of a current portion being processed, identifying a portion of the context information that corresponds to the next sub-portion, converting the portion from a first format to a second format, and writing the portion into the non-volatile memory.

The disclosed technology relates to solutions for improving a firmware update mechanism and in particular, for improving a firmware update mechanism of a power distribution board by utilizing different boot procedures. A process of the disclosed technology can include steps for receiving, at a microcontroller, a firmware update, wherein the firmware update is transmitted by a computer powered by a power distribution board associated with the microcontroller, initiating, by the microcontroller, a warm boot procedure using the firmware update, and marking the warm boot procedure as successful if a message received from the computer indicates that the firmware update is successful. In some aspects, the process can further include steps for determining a power reset of the computer, initiating, by the microcontroller, a cold boot procedure using the firmware update, and marking the firmware update as proven if the message from the computer indicates that the firmware update is successful. Systems and machine-readable media are also provided.

A cache and memory coherent system includes multiple processing chips each hosting a different subset of a shared memory space and one or more routing tables defining access routes between logical addresses of the shared memory space and endpoints that each correspond to a select one of the multiple processing chips. The system further includes a coherent mesh fabric that physically couples together each pair of the multiple processing chips, the coherent mesh fabric being configured to execute routing logic for updating the one or more routing tables responsive to identification of a first processing chip of the multiple processing chips hosting a defective hardware component, the update to the routing tables being effective to remove all access routes having endpoints corresponding to the first processing chip.