G06F11/184

Technologies for efficient reliable compute operations for mission critical applications
11157374 · 2021-10-26 · ·

Technologies for efficiently providing reliable compute operations for mission critical applications include a reliability management system. The reliability management system includes circuitry configured to obtain conclusion data indicative of a conclusion made by each of two or fewer compute devices of a host system. The conclusion data from each compute device pertains to the same operation. Additionally, the circuitry is configured to identify whether an error has occurred in the operation of each compute device, determine, in response to a determination that an error has occurred, a severity of the error, and cause the host system to perform a responsive action as a function of the determined severity of the error.

METHOD AND APPARATUS FOR IMPLEMENTING DATA CONSISTENCY, SERVER, AND TERMINAL
20210320977 · 2021-10-14 ·

In this application, a client generates an operation for data, and records the operation as a log entry. The client sends the log entry to nodes comprising a leader and a plurality of followers. The client receives a plurality of response messages in a preset time period, where the response messages indicate that the operation is successfully performed. Different response messages are from different nodes. When a total quantity of the plurality of response messages received by the client in the preset time period is greater than half of a quantity of nodes, the client determines that the operation is successfully performed.

SYSTEM RECOVERY USING A FAILOVER PROCESSOR

Techniques for system recovery using a failover processor are disclosed. A first processor, with a first instruction set, is configured to execute operations of a first type; and a second processor, with a second instruction set different from the first instruction set, is configured to execute operations of a second type. A determination is made that the second processor has failed to execute at least one operation of the second type within a particular period of time. Responsive to determining that the second processor has failed to execute at least one operation of the second type within the particular period of time, the first processor is configured to execute both the operations of the first type and the operations of the second type.

Touch instruction

An apparatus comprising data processing circuitry for processing data in one of a plurality of operating states, an instruction decoder for decoding instructions and error checking circuitry for performing error checking operations. In response to a touch instruction being decoded by the instruction decoder, error checking operation is performed on selected architectural state. The architectural state is architecturally inaccessible to the operating state. As a result of the touch instruction, the architectural state remains unchanged, at least when no error is detected.

REDUNDANCY CONTROL DEVICE FOR AIRCRAFT
20210281265 · 2021-09-09 ·

The redundancy control device includes three controllers that output status signals, a majority voting circuit to which a first voltage or a second voltage is supplied as an output signal through an output line of each controller, a switch provided in each output line, a voltage supply unit provided for each output line to supply the second voltage to the output line when the first voltage is lost, a latch circuit provided for each output line to latch the second voltage when the second voltage is supplied thereto and continue to output the second voltage, a comparison circuit provided for each controller to output a comparison signal based on a comparison of the status signals, and a switch control unit provided for each switch to outputs a switch signal to the switch in response to the comparison signal from the comparison circuit.

Fault tolerant computer systems and methods establishing consensus for which processing system should be the prime string

Systems and methods for fault tolerant computing in accordance with various embodiments of the invention are disclosed. Fault tolerant computer systems in accordance with a number of embodiments of the invention include multiple processing systems supervised by a Fault Management Unit (FMU). The FMU can build a representation of the state of all of the multiple processing systems and then determines which of the processing systems to utilize to perform a particular function based upon this state representation.

Data processing using proof-of-transfer

An improved blockchain implementation that uses proof-of-transfer to overcome the technical deficiencies of proof of work and proof-of-stake implementations is described herein. For example, the proof-of-transfer process may include elements of a single-leader election sortition, but modified to cause base chain cryptocurrency committed for the purposes of the sortition to be transferred to a burn address or at least one reward address.

DISTRIBUTED COMPUTING IN A PROCESS CONTROL ENVIRONMENT

High availability and data migration in a distributed process control computing environment. Allocation algorithms distribute data and applications among available compute nodes, such as controllers in a process control system. In the process control system, an input/output device, such as a fieldbus module, can be used by any controller. Databases store critical execution information for immediate takeover by a backup compute element. The compute nodes are configured to execute algorithms for mitigating dead time in the distributed computing environment.

Processor for detecting and preventing recognition error

Provided is an image recognition processor. The image recognition processor includes a plurality of nano cores each configured to perform a pattern recognition operation and arranged in rows and columns, an instruction memory configured to provide instructions to the plurality of nano cores in a row unit, a feature memory configured to provide input features to the plurality of nano cores in a row unit, a kernel memory configured to provide a kernel coefficient to the plurality of nano cores in a column unit, and a difference checker configured to receive a result of the pattern recognition operation of each of the plurality of nano cores, detect whether there is an error by referring to the received result, and provide a fault tolerance function that allows an error below a predefined level.

Distributed computing in a process control environment

High availability and data migration in a distributed process control computing environment. Allocation algorithms distribute data and applications among available compute nodes, such as controllers in a process control system. In the process control system, an input/output device, such as a fieldbus module, can be used by any controller. Databases store critical execution information for immediate takeover by a backup compute element. The compute nodes are configured to execute algorithms for mitigating dead time in the distributed computing environment.