Patent classifications
G06F11/2005
High reliability fault tolerant computer architecture
A fault tolerant computer system and method are disclosed. The system may include a plurality of CPU nodes, each including: a processor and a memory; at least two IO domains, wherein at least one of the IO domains is designated an active IO domain performing communication functions for the active CPU nodes; and a switching fabric connecting each CPU node to each IO domain. One CPU node is designated a standby CPU node and the remainder are designated as active CPU nodes. If a failure, a beginning of a failure, or a predicted failure occurs in an active node, the state and memory of the active CPU node are transferred to the standby CPU node which becomes the new active CPU node. If a failure occurs in an active IO domain, the communication functions performed by the failing active IO domain are transferred to the other IO domain.
System and method for improved power utilization in hart field instrument transmitters to support bluetooth low energy
A method includes determining, by a field instrument in an industrial process and control system, a Highway Addressable Remote Transducer (HART) mode of the field instrument. The method also includes, upon a determination, by the field instrument, that the HART mode is a HART On Demand mode, listening for a HART data signal from a HART master device; when the HART data signal is detected, communicating with the HART master device according to a HART protocol; and when the HART data signal is not detected, diverting a current supply allocated for HART communication to a BLUETOOTH Low Energy (BLE) transceiver for use in BLE communication, and communicating according to a BLE protocol.
Data encoding using spare channels in a memory system
Implementations of encoding techniques are disclosed. The encoding technique, such as a Data bus Inversion (DBI) technique, is implementable in a vertically-stacked memory module, but is riot limited thereto. The module can be a plurality of memory integrated circuits which are vertically stacked, and which communicate via a bus formed in one embodiment of channels comprising Through-Wafer Interconnects (TWIs), but again is not limited thereto. One such module includes spare channels that are normally used to reroute a data signal on the bus away from faulty data channels. In one disclosed technique, the status of a spare channel or channels is queried, and if one or more are unused, they can be used to carry a DBI bit, thus allowing at least a portion of the bus to be assessed in accordance with a DBI algorithm. Depending on the location and number of spare channels needed for rerouting, DBI can be apportioned across the bus in various manners. Implementations can also be used with other encoding techniques not comprising DBI.
Adaptive private network with path maximum transmission unit (MTU) discovery process
Systems and techniques are described for a path maximum transmission unit (MTU) discovery method that allows the sender of IP packets to discover the MTU of packets that it is sending over a conduit to a given destination. The MTU is the largest packet that can be sent through the network along a path without requiring fragmentation. The path MTU discovery method actively probes each sending path of each conduit with fragmentation enabled to determine a current MTU and accordingly increase or decrease the conduit MTU. The path MTU discovery process is resilient to errors and supports retransmission if packets are lost in the discovery process. The path MTU discovery process is dynamically adjusted at a periodic rate to adjust to varying network conditions.
Identifying valid data after a storage system recovery
Staging data on a storage element integrating fast durable storage and bulk durable storage, including: receiving, at a storage element integrating fast durable storage and bulk durable storage, a data storage operation from a host computer; storing data corresponding to the data storage operation within fast durable storage in accordance with a first data resiliency technique; and responsive to detecting a condition for transferring data between fast durable storage and bulk durable storage, transferring the data from fast durable storage to bulk durable storage in accordance with a second data resiliency technique.
DATA ENCODING USING SPARE CHANNELS IN A MEMORY SYSTEM
Implementations of encoding techniques are disclosed. The encoding technique, such as a Data bus Inversion (DBD technique, is implementable in a vertically-stacked memory module, but is not limited thereto. The module can be a plurality of memory integrated circuits which are vertically stacked, and which communicate via a bus formed in one embodiment of channels comprising Through-Wafer Interconnects (TWIs), but again is not limited thereto. One such module includes spare channels that are normally used to reroute a data signal on the bus away from faulty data channels. In one disclosed technique, the status of a spare channel or channels is queried, and if one or more are unused, they can be used to carry a DBI bit, thus allowing at least a portion of the bus to be assessed in accordance with a DBI algorithm. Depending on the location and number of spare channels needed for rerouting, DBI can be apportioned across the bus in various manners. Implementations can also be used with other encoding techniques not comprising DBL
SYSTEM AND METHOD FOR FAULT IDENTIFICATION AND FAULT HANDLING IN A MULTIPORT POWER SOURCING DEVICE
System and method for fault identification and fault handling in MPSD are provided. The system includes: a multi-port power sourcing device including multiple ports, a master is configured to: send a slave discovery request to multiple slave ports, receive a slave discovery response from the multiple slave ports; reset the watchdog timer in the multiple ports by sending watchdog refresh instruction periodically; each of the multiple ports experience watchdog timer timeout upon failing to receive the watchdog refresh instruction, generate their corresponding port reset upon watchdog timer timeout, to resolve one or more faults associated with the corresponding port; the multiple ports include a role change staggered timer which is triggered upon the corresponding watchdog timer timeout, and reset upon receiving the watchdog refresh instruction from master; the slave ports for which role change staggered timer times out first, changes the role to start functioning as the new master port.
SEMICONDUCTOR DEVICE AND METHOD FOR PROTECTING BUS
The master interface generates copy data by copying the first data, and generates an error detection code based on the copy data. The protocol conversion unit generates the second data by converting the first data from the first protocol to the second protocol. The slave interface detects errors in the copy data based on the error detection code. The slave interface also generates the first verification data by performing a conversion from one of the first protocol or the second protocol to the other for one of the second data or copy data. In addition, the slave interface compares the second verification data with the first verification data, using the other of the second data or copy as the second verification data.
Dynamically Verifying Ingress Configuration Changes
Dynamically verifying ingress configuration changes is provided. A temporary ingress controller configuration is generated for an ingress configuration change set contained in an ingress configuration change set dispatcher queue of an ingress controller pod. The temporary ingress controller configuration corresponding to the ingress configuration change set is loaded into a temporary ingress controller located in a temporary ingress controller pod of the computer. A health check is performed on the temporary ingress controller pod running the temporary ingress controller with the temporary ingress controller configuration corresponding to the ingress configuration change set. The temporary ingress controller configuration is used as a configuration for an ingress controller located in the ingress controller pod of the computer based on the health check indicating that the temporary ingress controller pod did not crash while running the temporary ingress controller with the temporary ingress controller configuration corresponding to the ingress configuration change set.
Selecting interfaces for device-group identifiers
In one embodiment, a computer networking device calculates a first hash value for an identifier of a group of computing devices, as well as a second hash value for the identifier of the group of computing devices, with each hash value being at least in part on the identifier of the group of computing devices and an identifier of the respective interface. The computer networking device may also analyze the first hash value with respect to the second hash value and select the first interface for association with the identifier of the group of computing devices based at in part on the analyzing. The computer networking device may further store an indication that the identifier of the group of computing devices is associated with the first interface.