Data encoding using spare channels in a memory system

Abstract

Implementations of encoding techniques are disclosed. The encoding technique, such as a Data bus Inversion (DBI) technique, is implementable in a vertically-stacked memory module, but is riot limited thereto. The module can be a plurality of memory integrated circuits which are vertically stacked, and which communicate via a bus formed in one embodiment of channels comprising Through-Wafer Interconnects (TWIs), but again is not limited thereto. One such module includes spare channels that are normally used to reroute a data signal on the bus away from faulty data channels. In one disclosed technique, the status of a spare channel or channels is queried, and if one or more are unused, they can be used to carry a DBI bit, thus allowing at least a portion of the bus to be assessed in accordance with a DBI algorithm. Depending on the location and number of spare channels needed for rerouting, DBI can be apportioned across the bus in various manners. Implementations can also be used with other encoding techniques not comprising DBI.

Claims

1. A method comprising: controlling a switching assembly of a memory device, the switching assembly coupled to at least first and second memory channels, each memory channel including a respective plurality of data channels for a respective word of data and one or more additional channels including at least one data bit inversion (DBI) channel; and in response to determining that at least one of the data channels of the first memory channel is faulty, rerouting a data signal of the faulty data channel to a DBI channel, and assigning a DBI channel of the second memory channel to operate as a DBI channel for a double word including the respective words of the first and second memory channels.

2. The method of claim 1, wherein each memory channel comprises 16 respective data channels for the respective word of data.

3. The method of claim 1, wherein the state of the assigned DBI channel operates to identify an inversion state of the 32 data channels of the double word.

4. The method of claim 3, wherein the 32 data channels are coupled to adjacent portions of a memory bus.

5. The method of claim 1, further comprising: encoding data of a first word to be transmitted through the first memory channel; and encoding data of a second word to be transmitted through the second memory channel.

6. The method of claim 5, wherein the encoding is different for the first word than for the second word.

7. The method of claim 6, wherein the encoding of the first and second words is determined in response to a DBI Inversion algorithm.

8. The method of claim 6, wherein the first and second words are to be transmitted within a common time interval, and wherein the encoding of the second word is determined in response to the data of the first word.

9. A stacked memory device, comprising: a logic circuit comprising DBI encoding circuitry, data channel remapping circuitry, and test circuitry to test for continuity of individual data channels interconnecting the logic circuit and multiple stacked memory devices; multiple stacked memory devices stacked with the logic circuit, the logic circuit and the multiple stacked memory devices interconnected with one another by through wafer interconnects (TWIs), to communicate multiple data, address, and control signals through respective memory data channels from a bus to one or more of the stacked memory devices; wherein the data TWIs include further include additional data channels; and wherein the data channel remapping circuitry is operable to map one or more of the additional data channels to function as either, a replacement data channel in place of a faulty data channel, or a DBI indicator channel carrying a signal identifying whether data transmitted on a first group of data channels is inverted; wherein in response to a determination by the test circuitry that an individual data channel is faulty, the logic circuitry performs functions including rerouting a data signal of the faulty data channel to a DBI channel, and assigning a DBI channel of a second memory data channel to operate as a DBI channel for a double word including respective words of first and second memory data channels.

10. The stacked memory device of claim 9, wherein the first group of data channels is configured to carry a word of data.

11. The stacked memory device of claim 9, wherein the first group of data channels includes 16 data channels.

12. A stacked memory device, comprising: a logic circuit comprising DBI encoding circuitry and data channel remapping circuitry; multiple stacked memory devices stacked with the logic circuit, the logic circuit and the multiple stacked memory devices interconnected with one another by through wafer interconnects (TWIs), to communicate multiple data, address, and control signals through respective channels from a bus to one or more of the stacked memory devices; wherein the data TWIs include further include additional data channels; and wherein the data channel remapping circuitry is operable to map one or more of the additional data channels to function as either, a replacement data channel in place of a faulty data channel, or a DBI indicator channel carrying a signal identifying whether data transmitted on a first group of data channels is inverted; wherein a determination by the test circuitry that an individual data channel of the first group of data channels is defective, causes the channel mapping circuitry to remap an additional data channel from being a DBI indicator channel for the first group of data channels to a data channel replacing the defective data channel.

13. The stacked memory device of claim 12, wherein the channel mapping circuitry is further operable to remap a DBI indicator channel for a second group of data channels to serve as a DBI indicator channel for both the first and second groups of data channels.

14. The stacked memory device of claim 13, wherein the first and second groups of data channels are adjacent channels along the bus.

15. The stacked memory device of claim 12, wherein remapping an additional data channels from being a DBI indicator channel comprises disabling the defective data channel and re-mapping the defective data channel and subsequent data channels in the first group of data channels.

16. The stacked memory device of claim 12, wherein remapping an additional data channel from being a DBI indicator channel comprises disabling the DBI encoder for that additional data channel.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 illustrates a block diagram of a data transmission system.

(2) FIGS. 2A and 2B illustrates a block diagram and a data table illustrating a minimum transitions data bus inversion (DBI) technique.

(3) FIG. 3 illustrates a system in which RAM ICs are used in conjunction with a logic integrated circuit having circuitry implementing functions traditionally present on RAM ICs.

(4) FIG. 4 illustrates how the system of FIG. 3 can be implemented using a vertically-stacked memory module on a printed circuit board.

(5) FIG. 5 illustrates, in accordance with an embodiment of the invention, improved logic circuitry implementable in the system of FIGS. 3-4 for assessing the status of a spare channel to assist in the application of DBI.

(6) FIG. 6A illustrates how a data signal designated for a faulty data channel is rerouted to a spare channel using a switching matrix.

(7) FIG. 6B illustrates that if the spare channel of FIG. 6A is not used for rerouting, that channel may be used to carry a DBI bit.

(8) FIG. 6C illustrates the switching network useable to reroute to a spare channel (i) a data signal away from a faulty data channel or (ii) a DBI bit in the event that no data channel is faulty.

(9) FIGS. 7A and 7B illustrate an alternative switching network useable to reroute to a spare channel (i) a data signal away from a faulty data channel or (ii) a DBI bit in the event that no data channel is faulty.

(10) FIG. 8 illustrates application of the disclosed technique in the context of a larger bus having a plurality of spare channels, and specifically notes the DBI enable signals that the system may need to consider to apportion the bus from a DBI standpoint.

(11) FIGS. 9A-9E illustrate different manners in which the bus of FIG. 8 can be treated by the DBI control circuitry to implement DBI in different portions of the bus.

(12) FIG. 10 shows circuitry for implementing any of the variations of FIGS. 9A-9E.

DETAILED DESCRIPTION

(13) Implementations of encoding techniques are disclosed. The encoding technique, such as a Data bus inversion (DBI) technique, is implementable in a vertically-stacked memory module, but is not limited thereto. The module can be a plurality of memory integrated circuits which are vertically stacked, and which communicate via a bus formed in one embodiment of channels comprising Through-Wafer Interconnects (TWIs), but again is not limited thereto. One such module includes spare channels that are normally used to reroute a data signal on the bus away from faulty data channels. In one disclosed technique, the status of a spare channel or channels is queried, and if one or more are unused, they can be used to carry a DBI bit, thus allowing at least a portion of the bus to be assessed in accordance with a DBI algorithm. Depending on the location and number of spare channels needed for rerouting, DBI can be apportioned across the bus in various manners. Implementations can also be used with other encoding techniques not comprising DBI.

(14) FIG. 5 shows a general schematic for an improved vertically-stacked memory module 40′ generally constructed similarly to the module 40 shown in FIG. 4. As before, the improved module includes a logic IC 14 and a plurality of RAM ICs 16. A parallel bus, akin to bus 15 in FIGS. 3 and 4, carries a plurality of data channels in parallel between the logic IC 14 and the RAM ICs 16.sub.x. Only four data channels (DATA.sub.0-DATA.sub.3) are shown for simplicity. These data channels can carry data, addressing, or control signals, but are assumed to carry the data that is read front or written to the RAM IC16.sub.x, for simplicity. Given the vertically-stacked nature of the module 40′, the data channels are implemented using TWIs 83 and solder bumps 84, as was depicted in FIG. 4. However, the TWIs 83 are not shown in FIG. 5 for simplicity. As before, the data channels are bidirectional to allow reading and writing from and to the RAM ICs 16.sub.x.

(15) The data channels DATA.sub.i transfer original data signals Di between the logic IC 14 and the RAM ICs 16.sub.x. Generally speaking, and ignoring the distinction between original data signals Di and encoded data signals Xi for the moment, each data signal Di is designated for connection to a particular data channel DATA.sub.i, although this correspondence can vary if rerouting is necessary as explained further below. Absent such rerouting, and assuming a write to the RAM ICs 16.sub.x is occurring, output data path circuitry in the logic IC 14 produces original data signals D0-D3 in parallel, which are then ultimately transferred to data channels DATA.sub.0-DATA.sub.3 respectively, and ultimately to the D0-D3 input data path circuitry in the RAM ICs 16.sub.x. A reading operation occurs similarly, but in the opposite direction.

(16) Also illustrated in FIG. 5 is a spare channel, SPARE.sub.0. SPARE.sub.0 provides an alternative path for a data signal if its designated data channel is (or should become) faulty, for example, because a TWI in that data channel has poor connectivity. Like the data channels, the spare channels can comprise TWIs. Rerouting of the data signals occurs in conjunction with switching networks 122. Jumping ahead to FIG. 6A for a moment, notice via the dotted lines that the switching network 122 operating in the logic IC 14 and each of the RAM ICs 16.sub.x have rerouted a particular data signal D1 away front a faulty data channel (DATA.sub.1) to the spare channel (SPARE.sub.0). Such rerouting occurs under the control of rerouting circuitry 58 operable in the logic IC 14, and rerouting/DBI slave circuitry 108 operable in the RAM ICs 16.sub.x, whose functionality will be explained later.

(17) Returning to FIG. 5, note also the provision of a plurality of control channels (CNTR.sub.0-CNTR.sub.Y). The control channels allow for various control signals to be sent back and forth between the logic IC 14 and the RAM ICs 16.sub.x. Such control signals could comprise the memory-specific control signals discussed earlier (i.e., RAS, CAS, CS, or indicators thereof) or other control signals useful for generally controlling the operation of the module 40′. The nature of the control signals sent on the control channels can generally be dictated by system control circuit blocks 106 and 110 operating in the logic IC 14 and the RAM ICs 16.sub.x respectively. Because general control signals not involved with rerouting are not of particular interest to this disclosure, the details of system control circuit blocks 106 and 110 are omitted.

(18) The control channels CNTR.sub.0-CNTR.sub.Y may be time multiplexed such that they carry different control signals at different points in time. For example, the control channels may carry signals relevant to rerouting only upon initialization of the module 40′, or when it is otherwise warranted to make a continuity check of the TWI-based bus of data channels, which is discussed further below. The control channels CNTR.sub.0-CNTR.sub.Y may then carry memory-specific control signals (e.g., from system control circuit blocks 106 or 110) during periods of normal operation, for example.

(19) As just noted, the control channels CNTR.sub.0-CNTR.sub.Y may carry control signals relevant to rerouting around faulty data channels. Such control signals are generated at rerouting circuitry 58 in the logic IC 14, which generally functions during periods of initialization or testing to check for faulty data signals and to perform rerouting to an appropriate spare channel such as SPARE.sub.0. (The above-referenced patent applications discuss such operations further). In the example shown, rerouting circuitry 58 generates four switch control signals SW<3:0>, which are sent to the switching network 122 in the logic IC 14. As will be shown in further detail later, the switching network 122 then reroutes the data signal originally assigned to the faulty data channel onto the spare channel. Indication of these switch control signals SW<3:0> are also sent via the control channels CNTR.sub.0-CNTR.sub.Y to the rerouting/DBI slave circuitry 108 in the RAM ICs 16.sub.x, where they are stored and used to generate matching control signals SW<3:0> to control matching switching networks 122 in the RAM ICs 16.sub.x. The switch control signals can be transported across the control channels CNTR.sub.0-CNTR.sub.Y along one channel, many channels, in serial or parallel, in an encoded fashion, or in any appropriate fashion.

(20) FIG. 6A shows the operation of the switch control signals. In the example shown, rerouting circuitry 58 has determined that data channel DATA.sub.1 is faulty. This causes switch control signal. SW<1> in the illustrated example to go high. When this occurs, original data signal D1 is routed to the spare channel SPARE.sub.0 instead to its normally designated DATA1 signal, as shown by the dotted lines. Switching network circuitry 122 for accomplishing this result is shown in FIG. 6C. Continuing to ignoring the distinction between data signals Xi and Di for the moment, it is seen that the switch control signals SW<3:0> are sent to the control input of multiplexers 123. If a particular data signal Di does not have its corresponding switch control signal asserted (i.e, if SW<i>=0), then that data signal passes to DATA.sub.i. If a particular data signal (e.g., D1) does have its corresponding switch control signal asserted (e.g., if SW<1>=1), then that data signal passes to the spare channel, SPARE.sub.0. This same routing occurs for data traveling in the opposite direction.

(21) FIGS. 7A and 7B shows alternative switching network circuitry 122. In this embodiment, a faulty data channel is bypassed by sending the affected data signal (e.g., D1) and all subsequent data signals to the next available data channel and to the spare data channel. Thus, as shown by the dotted lines in FIG. 7A, data signal D1 is sent to DATA.sub.2, D2 is sent to DATA.sub.3, and D3 is sent to SPARE.sub.0. Offsetting the affected and subsequent data signals by one channel can be accomplished by using OR logic gates to process the switch control signals SW<3:0>, as shown in FIG. 7B. The operation of such logic gates should be self explanatory to one skilled in the art, and is thus riot further elaborated upon here.

(22) In the event that the spare channel, SPARE.sub.0, is not used for rerouting, it may be used for DBI in accordance with embodiments of the disclosed technique, as shown in FIG. 6B. As illustrated, the logic IC 14 and each of the RAM ICs 16.sub.x contains a DBI codec 120 for producing encoded data signals Xi from the original data signals Di, and for decoding the encoded data signals Xi back into the original data signals Di. First Input/Outputs (I/Os) 300 couple to the original data signals, while second I/Os 302 couple to the encoded data signals and to the DBI hit (see FIG. 5). So configured, the DBI codec 120 when enabled either encodes the original data signals at the first I/Os 300 into encoded data signals at the second I/Os 302 and issues a corresponding DBI bit at the DBI I/O 302, or decodes encoded data signals at the second I/Os 302 into original data signals at the first I/Os 300 in conjunction with a DBI bit received at the DBI I/O 302. The DBI codec 120 can run any number of DBI algorithms as was discussed in the Background of this disclosure, and no particular DBI algorithm is important to the disclosed technique. DBI encoding and decoding circuitry is well known, and an example can he found in the above-mentioned '779 application.

(23) Regardless of the DBI algorithm employed in DBI codec 120, the algorithm assesses the original data signals D0-D3 and decides whether to invert all or part of those signals. If the DBI algorithm's assessment reveals a benefit to inverting all or a portion of the original data signals D0-D3, then all or a portion of those data signals are inverted to produce encoded data signals X0-X3, and a DBI bit, DB10, is issued. if the algorithm decides that there is no benefit to inversion, then the original data signals D0-D3 are simply passed as signals X0-X3 without inversion, and the DBI bit is not asserted for that data set.

(24) Whether DBI can be enabled is determined by DBI control circuitry 104. DBI control circuitry 104 essentially determines whether the spare channel, SPARE.sub.0, is being used because it is needed for rerouting. If SPARE.sub.0 is not being used, DBI control circuitry 104 will enable the DBI codec 120 to apply the DBI algorithm to the original data signals D0-D3 to produce encoded data signals X0-X3 which are forwarded to data channels DATA.sub.0-DATA.sub.3, and to provide the DBI bit to SPARE.sub.0. If SPARE.sub.0 is being used because it is necessary to reroute one of the data signals away from a faulty data channel, DBI control circuitry 104 disables the DBI codec 120 such that the original data signals D0-D3 merely flow through the DBI codec without analysis and without generation of the DBI bit. The switching network 122 then reroutes the data signal affected by the reroute to SPARE.sub.0, and the other data signals pass to their respective data channels DATA.sub.0-DATA.sub.3 as discussed previously.

(25) To do this, the DBI control circuitry 104 receives an indication of the spare channel status from the rerouting circuitry 58 in the logic IC 14. Specifically, the rerouting circuitry 58 contains spare channel status circuitry 102, which comprises a means for storing an indication of the status of the spare channel. In one simple embodiment, spare channel status circuitry 102 can comprise a four-bit storage register for the switch control signals SW<3:0>, which values are then sent to the DBI control circuitry 104. The DBI control circuitry 104 then analyzes the switch control signals SW<3:0> to determine whether the spare channel is being used for rerouting or not, and whether the. DBI codec 120 can be enabled.

(26) One simple implementation of the DBI control circuitry 104 is shown in FIGS. 6C and 7B, and comprises a NOR gate. Should any of the switch control signals SW<3:0> be asserted (e.g., SW<1>=1), indicating a faulty data channel and hence the need for rerouting to the spare channel, the NOR gate outputs a 0 as the DBI enable signal (DBI_en), which disables the DBI codec 120 from applying its algorithm to the data signals D; hence, the original data signals D0-D3 flow through the DBI codec 120 unaffected. Additionally, disabling the DBI enable signal disables pass gate 124, which prevents the DBI bit, DBI0, from passing from the DBI codec 120 to the spare channel. At the same time, the assertion of one of the switch control signal (e.g., SW<1>) causes the affected data signal (i.e., D1) to be rerouted away front its designate data channel (i.e., DATA.sub.1), either by routing that data signal to the spare channel, SPARE.sub.0 (FIG. 6C), or by shifting the affected and subsequent data signals (FIG. 7B), as discussed previously. Such rerouting is shown in dotted lines in FIGS. 6A and 7A.

(27) Should none of the switch control signals be asserted (i.e., SW<3:0>=0), meaning that rerouting of data is not necessary, then the NOR gate of DBI control circuitry 104 outputs a 1 as the DBI enable signal, DBI_en. This enables the DBI codec 120 to apply its algorithm to the original data signals D0-D3, to produce encoded data signals X0-X3, and to generate a corresponding DBI bit, DBI0. Additionally, enabling the DBI enable signal enables pass gate 124, which allows the DBI bit, DBI0, to pass to the otherwise unused spare channel, SPARE.sub.0. At the same time, the failure to assert any of the switch control signals SW<3:0> causes the switching network 122 to pass the encoded data bits X0-X3 to their respective data channels DATA.sub.0-DATA.sub.3. Such routing is shown in dotted lines in FIG. 6B.

(28) In the technique as described thus far, the logic IC 14, via operation of rerouting circuitry 58 and DBI control 104, comprises the master controllers for rerouting and DBI enablement. The RAM ICs 16.sub.x, by contrast, contain mere corresponding slave controllers, i.e., rerouting/DBI slave circuitry 108. As mentioned earlier, the rerouting/DBI slave circuitry 108 can receive and store rerouting signals from the rerouting circuitry 58 in the logic IC 14 via control channel(s) CNTR.sub.0-CNTR.sub.Y. The DBI enable signal, DBI_en, can also be transmitted to the RAM ICs 16.sub.x by the control channel(s) CNTR.sub.0-CNTR.sub.Y, but it may be more convenient instead to merely generate the DBI enable signal at the RAM ICs 16.sub.x from the switch control signals stored at the slave circuitry 108. To summarize, rerouting/DBI slave circuitry 108 essentially mimics the operation of the rerouting circuitry 58 and DBI control circuitry 104 operable in the logic IC 14 so that the DBI codecs 120 and the switching networks 122 in both the logic IC 14 and the RAM ICs 16.sub.x can be controlled similarly.

(29) FIGS. 8-10 show the extension of the disclosed technique to a more realistic 32-bit data bus. As shown in FIG. 8, a typical TWI-based bus 15 in a memory module 40′ comprises 32 data channels (DATA.sub.0-DATA.sub.31) and four spare channels (SPARE.sub.0-3). When so configured, one spare channel is typically designated to serve as the rerouting channel for a given eight bits of the data channels, but this need not always be the case; spares may service more than a single byte. But in the simple case described below, SPARE.sub.0 is designated as the rerouting path should any of data channels DATA.sub.0-7 prove faulty; SPARE.sub.1 is similarly designated for DATA.sub.8-15; etc.

(30) A larger bus with a plurality of spare channels increases the sophistication with which DBI algorithms can operate, assuming that at least one spare channel is not being used for rerouting. For example, and as shown in FIG. 8, a number of DBI enable signals can be employed to apply DBI to particular portions of the data signals. For example, DBI_en<0> can enable the DBI codec 120 to apply a DBI algorithm to the group of data signals presented to data channels DATA.sub.0-7, i.e., the first byte of the 32-bit data bus 15; DBI_en<1> can apply the DBI algorithm to data signals presented to the group of data channels DATA.sub.8-15; etc. In this way, the bus 15 can he apportioned to provide an independent DBI analysis to four different bytes of the bus. This renders four different DBI bits, DBI0-3: DBI0, corresponding to encoding data signals X0-X7 designated for DATA.sub.0-7; DBI1, corresponding to encoded data signals X8-X15 designated for DATA.sub.8-15, etc. These DBI bits, DBI0-3, can generally be sent on their respective spare channels SPARE.sub.0-3, as explained in more detail below.

(31) Apportioning the bus 15 in this manner for DBI purposes adds complexity, but can improve the benefits of DBI. This is because dividing the bus into groups of data signals, and applying DBI to each group independently and generating a DBI bit for each portion independently, reduces power consumption when compared to applying DBI to a larger, undivided bus (which undivided bus would only require one DBI bit). Applying DBI to an apportioned bus is addressed in the following references, which are submitted with the Information Disclosure Statement filed with this disclosure: U. Narayanan, “Enchanced Bus Invert Encodings for Low-Power,” IEEE, Circuits and Systems, vol. 5, pgs 25-28 (2002); Y. Shin, “Reduction of bus transitions with partial bus-invert coding,” Electronic Letters, vol. 34, no. 7 (Apr. 2, 1998); and M. Stan & W. Burleson, “Bus-Invert Coding for Low Power I/O,” pgs. 1-20 (1999).

(32) DBI can also operate to assess portions of the bus 15 larger than a byte. For example, the DBI codec 120 can be enabled to apply DBI to a group comprising a word's worth of data, i.e., 16 bits. This can occur by providing two different DBI enable signals to the DBI codec 120: DBI_en<T>, which enables the DBI codec 120 to apply its algorithm to the top word of data, i.e., to the data signals presented to data channels DATA.sub.0-15; and DBI_en<B>, which similarly enables the DBI codec 120 to apply DBI to the bottom word of data to be presented to DATA.sub.16-31. Apportioning the bus in this manner requires two DBI bits, DBI_T and DBI_B, to be carried on the spare channels.

(33) Finally, DBI can also operate on the entire double word of data, i.e., a single group of all 32 data signals. The DBI codec 120 can be enabled to do so via signal DBI_en<W>, which assesses DBI based on the whole of the data channels. If DBI is applied to the entire bus, only one DBI bit, DBI_W, would be required, which could be carried on any free spare channel.

(34) The ability to apply DBI at these various levels of bus apportionment improves the flexibility with which DBI can be applied to the data bus 15. However, since the DBI bit or bits are sent over the spare channels, the options for applying DBI will be constrained depending on which spare channels are needed for rerouting. The DBI control circuitry 104 therefore, after consideration of the status of the switch control signals to understand where rerouting is occurring along the bus 15, should issue appropriate DBI enable signals to apportion the bus for DBI purposes without inhibiting rerouting. Various conditions illustrating such options are shown in FIGS. 9A-9E.

(35) FIG. 9A illustrates a first condition in which none of the data channels DATA.sub.0-31 has experienced a continuity error. In this circumstance, all of the data channels DATA.sub.0-31 carry their designated encoded data signals X1-X31, and all of the spare channels SPARE.sub.0-3 are available to carry a DBI bit, and this can occur in different ways depending on the designer's choice tor apportioning the bus. In the option of column A, the bus is apportioned into four bytes, with DBI being applied to each byte. This requires the DBI control circuitry 104 to generate four codec enable signals, DBI_en<0:3>. Enabling the codec in this manner causes the codec 120 to generate four DBI bits: DBI0 associated with encoded data signals X0-X7, DBI1 associated with X8-X15; DBI2 associated with X16-X23; and DBI3 associated with X24-X31.

(36) In the option of column B, DBI can be apportioned to the top and bottom words of data. This requires the use of enable signals DBI_en<T> and DBI_en<B>, and the generation of two DBI bits: DBI_T associated with the top word of encoded data signals X0-X15; and DBI_B associated with X16-31. Here, DBI_T can be sent on spare channel SPARE.sub.1 (or SPARE.sub.0) and DBI_B can be sent on spare channel SPARE.sub.3 (or SPARE.sub.2), with the other spare channels remaining unused.

(37) In the option of column C, the bus is not apportioned, and DBI is applied to all 32 data signals, requiring the use of enable signal DBI_en<W> and the generation of only a single DBI bit, DBI_W, which can be sent on any of the spare channels, but which is shown in FIG. 9A as sent on SPARE.sub.3. Because none of the data channels are faulty, the other spare channels go unused.

(38) FIG. 9B illustrates a second condition in which only one of the data channels has experienced a continuity error and requires rerouting. This error is illustrated as occurring in the first byte of data, i.e., in one of data channels D.sub.0-7. In this circumstance, the spare channel associated with the affect byte, SPARE.sub.0, will need to carry the affected data signal. In option A, DBI is simply not performed on the faulty byte, i.e., DBI_en<0> is not issued by the DBI control circuitry 104, and DBI0 is not generated by the DBI codec 120. Instead, the original data signals D0-D7 pass to their respective data channels DATA.sub.0-7, expect for the data signal designated for the faulty channel, which is sent to the spare channel SPARE.sub.0. In short, the DBI codec 120 is bypassed for the first byte of data. Because the remaining spare channels are unused, they can be used for DBI on a byte basis. Thus, enable signals DBI_en<1:3> are issued, which causes codec 120 to encode the original data signals D8-D31 into encoded signals X8-X31, and which generates DBI bits DBI1, DB2, and DBI3 for each byte. These DBI bits are carried by the free spare channels SPARE.sub.1-3, respectively.

(39) All other options B, C, and D of FIG. 9B perform DBI on the entirety of the 32 data signals, but with different apportionments. In option B, DBI is performed on the top word, i.e., the one containing the faulty data channel. More specifically, DBI control circuitry 104, realizing from the switch control signal that SPARE.sub.0 must carry the affected encoded data signal, issues DBI_en<T> to perform DBI on the original data signals D0-D15 to produce encoded data signals X0-X15. The resulting DBI bit, DBI_T, is sent to the other spare channel in the word. SPARE.sub.1. In option B, the bottom two bytes are apportioned on a byte basis, and handled the same as option A, with byte-specific DBI bits, DBI2 and DBI3, being carried by the otherwise unused spare channels, SPARE.sub.2 and SPARE.sub.3.

(40) In option C, DBI is performed on a word basis. This requires issuing enable signals DBI_en<T> and DBI_en<B>, which enables the codec 120 to produced encoded data signals X0-X15 and X16-X31, and their associated DBI bits, DBI_T and DBI_B, respectively. As with option B, the faulty encoded data signal continues to be carried by SPARE.sub.0, with the other spare in the word, SPARE.sub.1, carrying DBI_T. On the bottom word, the DBI bit, DBI_B, is sent to one of the bottom word spare channels (e.g, SPARE.sub.3) and the other spare channel (SPARE.sub.2) is unused. Option C thus differs from option B in that the DBI apportionment is applied to equally-sized portions of the data bus, i.e., two words, instead of one word and two bytes.

(41) In option D, DBI is applied to all 32 bits, similar to what occurred in option C of FIG. 9A, with the only difference being that the affected encoded data signal is rerouted to SPARE.sub.0. As shown in FIG. 9B, the remaining two spare channels SPARE.sub.1 and SPARE.sub.2, i.e., those carrying neither DBI_W nor the affected encoded data signal, remain unused.

(42) FIG. 9C illustrates a third condition in which two of the data channels have experienced continuity errors and require rerouting. This third condition can comprise two different scenarios in which the faulty data channels occur in different words (III) or in the same word (III′). Turning to scenario III first, option A is essentially similar to option A in FIG. 9B, in that DBI is applied on a byte basis but simply not performed on the two faulty bytes. In option B, DBI is performed on all data signals, but on a word basis. Therefore, one spare channel in each word carries the rerouted encoded data signal with the other spare channel carrying the DBI bit (DBI_T or DBI_B) for the word. Option C performs DBI on all 32 bits. One spare channel carries the DBI bit for the double word (DBI_W), two other spare channels carry the rerouted encoded data signals, and the remaining spare channel goes unused.

(43) Scenario III′, in which both errors occur in the same word, is essentially the same as Scenario III just discussed. However, in option B, where DBI assessment occurs on a word basis, there is no spare channel in the top byte to carry the DBI bit for the top byte (i.e., DBI_T). Therefore, in this scenario, DBI_T bit is routed to the available spare channel in the bottom word (i.e., SPARE.sub.2). Although this generally violates the preference to keep a particular DBI bit in proximity to its associated data, it requires no particular technical challenge to so reroute the DBI bit.

(44) FIG. 9D illustrates a fourth condition in which three of the data channels have experienced continuity errors requiring rerouting. Option A is similar to option A as discussed in FIGS. 9B and 9C, in that DBI is merely not applied to the bytes having the affected data, leaving only one byte (that byte not requiring rerouting) to benefit from DBI. Option B varies from option A in that DBI is applied to a word of data, instead of a mere byte. Here, DBI is ignored in the top word (the byte having two errors), and the spare channels associated with that word merely carry the rerouted original data signals. DBI is however applied to the bottom word, with the spare in the faulty byte carrying the affected encoded data signal, and the remaining spare carrying the DBI bit for the bottom word (DBI_B). In option C, DBI is assessed for all 32 bits. The single DBI bit from this analysis, DBI_W, is issued in the only byte not experiencing an error, and thus whose spare channel is not already carrying rerouted encoded data.

(45) FIG. 9E illustrates a fifth condition in which all bytes of data are experiencing a continuity error. In this case, all of the spare channels must be used to reroute the data signal from its associated byte. Accordingly, there is no room left to carry any DBI bits. The DBI control circuitry 104 thus issues no DBI enable signals, and the DBI codec 120 is bypassed.

(46) Circuitry for implementing the various conditions illustrated in FIG. 9A-9E is shown generically in FIG. 10. As was discussed earlier, the DBI control circuitry 104 receives an indication of the status of the various spare channels from storage 102, and generates DBI enable signals as appropriate. DBI control circuitry 104 would normally comprise a network of logic gates configured to affect DBI in accordance with the various conditions set birth in FIGS. 9A-9E, and in accordance with the particular option within each condition that the designer finds suitable for a given environment. Given the wide array of potential DBI encoding options just discussed, one skilled in the art will realize that the logic network of DBI control circuitry 104 will be implementation specific, and a routine matter to construct once the designer's options have been finalized.

(47) The switching network 122 will likewise be implementation specific and will depend on the DBI options chosen. When applied to a more complex bus such as that shown in FIG. 10, one skilled in the art will realize that the multiplexers in the switching network 122 may require more complex logic function at their inputs, or may require multiple inputs or multiple levels of multiplexing. Designing such logic would be routine given the details provided in this disclosure once the particular options for DBI encoding have been finalized.

(48) Although conceived of in the context of a vertically stacked memory module, it should be noted that the inventive concepts disclosed herein are not necessarily limited to that environment.

(49) Any of these DBI algorithms mentioned above, or other data encoding algorithms more generally, can be used in the context of the disclosed embodiments of the invention. Additionally, other embodiments of the invention would not necessarily require operation of a data bus inversion algorithm. Instead, the codecs 120 could comprise other types of encoders and decoders (e.g., error detection, or error correction), and the DBI bit could more generally comprise an encoding indicator bit or bits (e.g., an error detection bit, or an error correction bit) consistent with the particular decoder. Thus, previously-existing or future-developed encoding/decoding schemes will also benefits from the disclosed techniques.

(50) While some implementations have been disclosed, it should be understood that the disclosed circuitry can be achieved in many different ways to the same useful ends as described herein. In short, it should be understood that the inventive concepts disclosed herein are capable of many modifications. To the extent such modifications fall within the scope of the appended claims and their equivalents, they are intended to be covered by this patent.