Patent classifications
G06F11/2038
Live browse cache enhacements for live browsing block-level backup copies of virtual machines and/or file systems
An illustrative approach accelerates live browse operations for block-level backup copies in a data storage management system. A cache storage area is maintained for locally storing and serving key data blocks, thus relying less on retrieving data on demand from backup copies. Live browse operations are used for populating the cache storage area for speedier retrieval during subsequent live browsing and/or file indexing of the same backup copy, and vice versa. The key data blocks cached while file indexing and/or live browsing an earlier backup copy help to pre-fetch corresponding data blocks of later backup copies, thus producing a beneficial learning cycle. The approach is especially beneficial for cloud and tape backup media, and is available for a variety of data sources and backup copies, including block-level backup copies of virtual machines (VMs) and block-level backup copies of file systems, including UNIX-based and Windows-based operating systems and corresponding file systems.
High availability for a relational database management system as a service in a cloud platform
A Relational Database Management System (“RDBMS”) as a service cluster may including a master RDBMS Virtual Machine (“VM”) node associated with an Internet Protocol (“IP”) address and a standby RDBMS VM node associated with an IP address. The RDBMS as a service (e.g., PostgreSQL as a service) may also include n controller VM nodes each associated with an IP address. An internal load balancer may receive requests from cloud applications and include a frontend IP address different than the RDBMS IP as a service addresses and a backend pool including indications of the master RDBMS VM node and the standby RDBMS VM node. A Hyper-Text Transfer Protocol (“HTTP”) custom probe may transmit requests for the health of the master RDBMS VM node and the standby RDBMS VM node via the associated IP addresses, and responses to the requests may be used in connection with a failover operation.
SYSTEMS AND METHODS TO FLUSH DATA IN PERSISTENT MEMORY REGION TO NON-VOLATILE MEMORY USING AUXILIARY PROCESSOR
A computing system that enables data stored in a persistent memory region to be preserved when a processor fails can include volatile memory comprising the persistent memory region, non-volatile memory, and a system on a chip (SoC). The SoC can include a main processor that is communicatively coupled to both the volatile memory and the non-volatile memory. The SoC can also include an auxiliary processor that is communicatively coupled to both the volatile memory and the non-volatile memory. The SoC can also include instructions that are executable by the auxiliary processor to cause the data in the persistent memory region of the volatile memory to be transferred to the non-volatile memory in response to a failure of the main processor.
Managing replication of computing nodes for provided computer networks
Techniques are described for providing managed computer networks, such as for managed virtual computer networks overlaid on one or more other underlying computer networks. In some situations, the techniques include facilitating replication of a primary computing node that is actively participating in a managed computer network, such as by maintaining one or more other computing nodes in the managed computer network as replicas, and using such replica computing nodes in various manners. For example, a particular managed virtual computer network may span multiple broadcast domains of an underlying computer network, and a particular primary computing node and a corresponding remote replica computing node of the managed virtual computer network may be implemented in distinct broadcast domains of the underlying computer network, with the replica computing node being used to transparently replace the primary computing node in the virtual computer network if the primary computing node becomes unavailable.
High reliability fault tolerant computer architecture
A fault tolerant computer system and method are disclosed. The system may include a plurality of CPU nodes, each including: a processor and a memory; at least two IO domains, wherein at least one of the IO domains is designated an active IO domain performing communication functions for the active CPU nodes; and a switching fabric connecting each CPU node to each IO domain. One CPU node is designated a standby CPU node and the remainder are designated as active CPU nodes. If a failure, a beginning of a failure, or a predicted failure occurs in an active node, the state and memory of the active CPU node are transferred to the standby CPU node which becomes the new active CPU node. If a failure occurs in an active IO domain, the communication functions performed by the failing active IO domain are transferred to the other IO domain.
Automated disaster recovery test verification
A Disaster Recovery (DR) verification process or system verifies readiness to execute a Disaster Recovery (DR) test. Such DR verification is automatically provided on a regular basis, with minimum impact on both a production and recovery environment. However, DR verification is only enabled at a time when no disaster recovery or DR testing of other sites is already under way. Configuration data needed for DR verification is constantly replicated from production to recovery, by dedicated data movers. DR verification allocates and configures recovery resources in an encapsulated environment, confirms successful their instantiation (such as boot up and network connections), and reports the outcome.
Electronic apparatus and boot method thereof
An electronic apparatus and a boot method thereof are provided. The electronic apparatus includes a first controller, a basic input output system (BIOS), and a second controller. The first controller is configured to receive a boot code and provides the boot code to the electronic apparatus for performing a boot operation. The BIOS is configured to provide the boot code. The second controller has at least one communication interface. The at least one communication interface is configured to be connected to at least one external apparatus. The at least one external apparatus provides a backup boot code to the second controller. When the boot operation performed by the electronic apparatus according to the boot code provided by the BIOS fails, the second controller replaces the first controller to receive the backup boot code and provides the backup boot code to enable the electronic apparatus to perform the boot operation.
MEDIATOR ASSISTED SWITCHOVER BETWEEN CLUSTERS
Techniques are provided for metadata management for enabling automated switchover. An initial quorum vote may be performed before a node executes an operation associated with metadata comprising operational information and switchover information. After the initial quorum vote is performed, the node executes the operation upon one or more mailbox storage devices. Once the operation has executed, a final quorum vote is performed. The final quorum vote and the initial quorum vote are compared to determine whether the operation is to be designated as successful or failed, and whether any additional actions are to be performed.
Real-time detection of and protection from malware and steganography in a kernel mode
A method for real-time detection of and protection from steganography in a kernel mode comprises detecting transmission of a file via a firewall, an operating system, or an e-mail system. A size of the file is determined. From a file system, a stored filesize of the file is retrieved. The determined size of the file is compared to the stored filesize of the file. Responsive to the determined size of the file being larger than the stored filesize of the file, steganography detection analytics are executed on the file. Responsive to the steganography detection analytics indicating presence of steganography in the file, a steganography remediation action is executed, and information is transmitted describing the steganography to a client device.
Robust Circuitry for Passive Fundamental Components
An apparatus is disclosed for making circuitry with passive fundamental components more robust. In example implementations, an apparatus includes at least one passive fundamental component and at least one redundant passive fundamental component. The apparatus also includes fault tolerant circuitry coupled to the at least one passive fundamental component and the at least one redundant passive fundamental component. The fault tolerant circuitry includes fault detection circuitry configured to detect a fault of the at least one passive fundamental component. The fault tolerant circuitry also includes component repair circuitry configured to disconnect the at least one passive fundamental component based on the fault.