A method for a computer or microchip with one or more inner hardware-based access barriers or firewalls that establish one or more private units disconnected from a public unit or units having connection to the public Internet and one or more of the private units have a connection to one or more non-Internet-connected private networks for private network control of the configuration of the computer or microchip using active hardware configuration, including field programmable gate arrays (FPGA). The hardware-based access barriers include a single out-only bus and/or another in-only bus with a single on/off switch.

Techniques for implementing high availability for persistent memory are provided. In one embodiment, a first computer system can detect an alternating current (AC) power loss/cycle event and, in response to the event, can save data in a persistent memory of the first computer system to a memory or storage device that is remote from the first computer system and is accessible by a second computer system. The first computer system can then generate a signal for the second computer system subsequently to initiating or completing the save process, thereby allowing the second computer system to restore the saved data from the memory or storage device into its own persistent memory.

A system may include a first node in a high-availability cluster; a second node in the high-availability cluster; a redundant interface between a network device and both the first node and the second node, wherein the redundant interface is associated with a redundancy group that designates one of the first node or the second node as a primary node in the high-availability cluster and that designates the other of the first node or the second node as a backup node in the high-availability cluster; a wireless interface of the first node, wherein the wireless interface is included in the redundant interface; and a wired interface of the second node, wherein the wired interface is included in the redundant interface.

Methods and systems for backing up and restoring sets of electronic files using sets of pseudo-virtual disks are described. The sets of electronic files may be sourced from or be stored using one or more different data sources including one or more real machines and/or one or more virtual machines. A first snapshot of the sets of electronic files may be aggregated from the different data sources and stored using a first pseudo-virtual disk. A second snapshot of the sets of electronic files may be aggregated from the different data sources subsequent to the generation of the first pseudo-virtual disk and stored using the first pseudo-virtual disk or a second pseudo-virtual disk different from the first pseudo-virtual disk.

An embodiment of an electronic apparatus may comprise one or more substrates, and a controller coupled to the one or more substrates, the controller to allocate a first secure portion of a pooled memory to a first instantiation of an application on a first node, and circuitry coupled to the one or more substrates and the controller, the circuitry to provide a failover interface for a second instantiation of the application on a second node to access the first secure portion of the pooled memory in the event of a failure of the first node. Other embodiments are disclosed and claimed.

A control system interface for a vehicle includes a primary processing unit and a secondary processing unit. The primary processing unit is configured to receive and process a trajectory generated by a trajectory computing unit for autonomous control of the vehicle. The secondary processing unit is configured to receive the trajectory concurrently with the primary processing unit, and to process the trajectory. Autonomous control of the vehicle is passed from the primary processing unit to the secondary processing unit in response to a fault condition with the primary processing unit.

Techniques for implementing high availability for persistent memory are provided. In one embodiment, a first computer system can detect an alternating current (AC) power loss/cycle event and, in response to the event, can save data in a persistent memory of the first computer system to a memory or storage device that is remote from the first computer system and is accessible by a second computer system. The first computer system can then generate a signal for the second computer system subsequently to initiating or completing the save process, thereby allowing the second computer system to restore the saved data from the memory or storage device into its own persistent memory.

Fault state transitions in an autonomous vehicle may include determining that a first node of a plurality of nodes has failed; determining, in response to the first node failing, a failure state; determining, based on the failure state, a configuration for the plurality of nodes excluding the first node; and applying the configuration.

The present invention relates to a method, system and computer program product for task failover in an unstable environment, wherein the unstable environment includes a plurality of reclaimable nodes. According to the method, it is monitored if any node of the plurality of reclaimable nodes is to be reclaimed. Whether a task on any node of the plurality of reclaimable nodes is recoverable is determined. Responsive to the task being recoverable, data of the recoverable task is stored. Responsive to a node being reclaimed and the task on the reclaimed node being recoverable, at least one associated task of at least one associated node of the reclaimed node is notified to wait.

Configuring an address-to-SC unit (A2SU) of each of a plurality of CPU chips based on a number of valid SC chips in the computer system is disclosed. The A2SU is configured to correlate each of a plurality of memory addresses with a respective one of the valid SC chips. In response to detecting a change in the number of valid SC chips, pausing operation of the computer system including operation of a cache of each of the plurality of CPU chips; while operation of the computer system is paused, reconfiguring the A2SU in each of the plurality of CPU chips based on the change in the number of valid SC chips; and in response to reconfiguring the A2SU, resuming operation of the computer system.