G06F11/326

MEMORY DEVICE WITH STATUS FEEDBACK FOR ERROR CORRECTION
20200394103 · 2020-12-17 ·

Methods, systems, and devices for a memory device with status feedback for error correction are described. For example, during a read operation, a memory device may perform an error correction operation on first data read from a memory array of the memory device. The error correction operation may generate second data and an indicator of a state of error corresponding to the second data. In one example, the indicator may indicate one of multiple possible states of error. In another example, the indicator may indicate a corrected error or no detectable error. The memory device may output the first or second data and the indicator of the state of error during a same burst interval. The memory device may output the data on a first channel and the indicator of the state of error on a second channel.

FACILITY MANAGEMENT SYSTEMS AND METHODS THEREOF

A facility management system comprises a server, a biometric identification unit, and a processing circuit. The server is configured to store a list of registered users, and biometric information and access rights pertaining to each registered users. The biometric identification unit is associated with the building equipment. The biometric identification unit is enabled to facilitate a user desiring access to the associated building equipment to scan at least one biometric parameter, and subsequent to scanning of the biometric parameter the biometric identification unit is configured to generate a scanned biometric information. The processing circuit is communicatively coupled with the server and the biometric identification unit, and is configured to: authenticate the user based on the biometric information and the scanned biometric information; determine the access rights for the authenticated user; and subsequently provide access to the authenticated user to operate the associated building equipment based on the determined access rights.

Batch testing system and method thereof

A batch testing system includes a test device, a plurality of machines to be tested and a server. The test device writes a BIOS with a RMT test to each machine to be tested, and starts each machine to be tested to run the RMT test, and then each machine to be tested writes a test result to a specific storage location in a baseboard management controller thereof. When entering an operating system, each machine to be tested reads and analyzes the test result at the specific storage location to output an analysis result, and then transmits the analysis result to the server through a network. The server receives and counts the analysis results transmitted by the machines to be tested. Therefore, the batch testing system can deploy the RMT test, and no intervention from operators is required in the whole process, which is suitable for the production testing stage.

Policy driven automation system for customer care

A policy driven automated micro-service system comprising: a data collector, an analyzer, a virtual function manager, a decision engine, and a portal; the virtual function manager in communication with at least one virtual function and configured to collect at least one of a data and a metric therefrom; the data collector in communication with the virtual function manager and configured to retrieve at least one of the data and the metric therefrom; the analyzer in communication with the data collector and configured to analyze at least one of the data and the metric collected by the data collector; and the decision engine in communication with the analyzer and the portal, the decision engine configured to initiate an action based on an analysis from the analyzer, wherein the action includes providing an instruction to reset a uCPE device, reload a software, reload a vendor virtual function, and engage a transport automation.

TRACE DATA ACQUISITION SYSTEM, TRACE DATA ACQUISITION METHOD, AND INFORMATION STORAGE MEDIUM
20200250069 · 2020-08-06 · ·

A trace data acquisition system, comprising: a plurality of industrial machines configured to sequentially process an object; and circuitry configured to: determine whether one of the plurality of industrial machines has satisfied a specific condition; and request another industrial machine to acquire trace data when the one of the plurality of industrial machines is determined to have satisfied the specific condition.

MEMORY SYSTEM AND DATA PROCESSING SYSTEM INCLUDING THE SAME
20200241984 · 2020-07-30 · ·

A memory system and a data processing system including the memory system may manage a plurality of memory devices. For example, the data processing system may categorize and analyze error information from the memory devices, acquire characteristic data from the memory devices and set operation modes of the memory devices based on the characteristic data, allocate the memory devices to a host workload, detect a defective memory device among the memory devices and efficiently recover the defective memory device.

IN-VEHICLE SYSTEM, WIRELESS COMMUNICATION DEVICE, AND CONTROL METHOD
20200226017 · 2020-07-16 · ·

An in-vehicle system performs wireless communication with electric power supplied from a battery mounted on a vehicle. The in-vehicle system includes a wireless communication unit configured to perform the wireless communication, a counting unit configured to count the number of resets that have occurred in the wireless communication unit; and an operation limiting unit configured to, when a predetermined power supply of the vehicle is off, limit the number of resets that occur in the wireless communication unit

Batch Testing System And Method Thereof
20200191865 · 2020-06-18 ·

A batch testing system includes a test device, a plurality of machines to be tested and a server. The test device writes a BIOS with a RMT test to each machine to be tested, and starts each machine to be tested to run the RMT test, and then each machine to be tested writes a test result to a specific storage location in a baseboard management controller thereof. When entering an operating system, each machine to be tested reads and analyzes the test result at the specific storage location to output an analysis result, and then transmits the analysis result to the server through a network. The server receives and counts the analysis results transmitted by the machines to be tested. Therefore, the batch testing system can deploy the RMT test, and no intervention from operators is required in the whole process, which is suitable for the production testing stage.

Intelligent storage media tray for identification and replacement of failed storage device in distributed storage systems

A storage server receives a control signal indicating that a specific storage device of a plurality of storage devices housed by a specific storage media tray has failed. The storage media tray is in turn housed by the specific storage server, which can house many such trays. In responsive to receiving the control signal, the server activates a visual fault indicator on an external display panel, indicating that the storage server contains a storage media tray housing a failed storage device. An external visual indicator on the specific storage media tray is activated to indicate that the specific storage media tray houses a failed storage device. The specific storage media tray activates an internal visual indicator identifying the specific storage device which has failed in the specific storage media tray. When the specific failed storage device has been replaced with a working storage device, the indicators are deactivated.

DYNAMIC RANDOM ACCESS MEMORY BUILT-IN SELF-TEST POWER FAIL MITIGATION
20200176072 · 2020-06-04 ·

Self-test and repair of memory cells is performed in a memory integrated circuit by two separate processes initiated by a memory controller communicatively coupled to the memory integrated circuit. To ensure that the repair process is completed in the event of an unexpected power failure, a first process is initiated by the memory controller to perform a memory Built-in SelfTest (mBIST) in the memory integrated circuit and a second process is initiated by the memory controller after the mBIST has completed to perform repair of faulty memory cells detected during the MBIST process. The memory controller does not initiate the repair process if a power failure has been detected. In addition, a repair time associated with the repair process is selected such that the repair time is sufficient to complete the repair process while power is stable, if a power failure occurs after the repair process has been started.