According to one embodiment, a semiconductor device includes a device. The device includes a decoder, a generation circuit, a register, and a modifier. The decoder analyzes a command of a received packet. The generation circuit generates a unique device number in accordance with information in the packet. The register holds the generated unique device number. The modifier updates and outputs the packet. When a packet issued by a host is a command packet, among broadcast packets which return to the host through one or more devices, for determining the unique device number, the command packet includes parameters of an initial value and final value of device number.

Methods of operating a memory system comprising a plurality of memory devices include loading respective sets of termination information to a subset of memory devices of the plurality of memory devices, and, for each memory device of the subset of memory devices, storing its respective set of termination information to an array of non-volatile memory cells of that memory device. For each memory device of the subset of memory devices, its respective set of termination information comprises address information of the memory system and one or more termination values associated with that address information.

A memory subsystem enables per device addressability (PDA) to target configuration commands to one of multiple memory devices that share a select line or buffer devices that share an enable line. The system includes a host and multiple memory devices that can be coupled over a command bus and a data bus. The devices include a configuration or mode register to store a value to indicate whether PDA enumeration is enabled. When enabled, the host can provide an enumeration identifier (ID) command via the command bus with a signal via the data bus to assign an enumeration ID. After assignment of the enumeration ID, the host can send PDA commands via the command bus with the enumeration ID, without a signal on the data bus. Devices only process PDA commands that match their assigned enumeration ID, enabling the setting of device-specific configuration settings without needing to use the data bus on every PDA command.

Memories that are configurable to operate in either a banked mode or a bit-separated mode. The memories include a plurality of memory banks; multiplexing circuitry; input circuitry; and output circuitry. The input circuitry inputs at least a portion of a memory address and configuration information to the multiplexing circuitry. The multiplexing circuitry generates read data by combining a selected subset of data corresponding to the address from each of the plurality of memory banks, the subset selected based on the configuration information, if the configuration information indicates a bit-separated mode. The multiplexing circuitry generates the read data by combining data corresponding to the address from one of the memory banks, the one of the memory banks selected based on the configuration information, if the configuration information indicates a banked mode. The output circuitry outputs the generated read data from the memory.

A storage system with a controller having a persistent memory interface to local memory is provided. The persistent memory can be used to store a logical-to-physical address table. A logical-to-physical address table manager, local to the controller or remote in a secondary controller, can be used to access the logical-to-physical address table. The manager can be configured to improve bandwidth and performance in the storage system.

Methods for termination of signal lines within a memory system include appointing a particular memory device of a plurality of memory devices to act as a termination device during a memory device operation on a memory device of the plurality of memory devices corresponding to a particular address of the memory system, wherein appointing the particular memory device to act as a termination device comprises storing termination information in the particular memory device corresponding to the particular address.

The disclosed technology is generally directed to data security. In one example of the technology, data is stored in a memory. The memory includes a plurality of memory banks including a first memory bank and a second memory bank. At least a portion of the data is interleaved amongst at least two of the plurality of memory banks. Access is caused to be prevented to at least one of the plurality of memory banks while a debug mode or recovery mode is occurring. Also, access is caused to be prevented to the at least one of the plurality of memory banks starting with initial boot until a verification by a security complex is successful. The verification by the security complex includes the security complex verifying a signature.

Provided are systems, methods, and computer-program products for enabling peer-to-peer communications between peripheral devices in a computing system. In various implementations, a host device in the computing system can read an address from a peripheral device included in the computing system. The host device can further configure an emulated peripheral device corresponding to the peripheral device, including writing the address to an emulated register of the emulated peripheral device. The host device can further initiate a virtual machine, including reading the address from the emulated register, initializing a page table for the virtual machine, and initiating a guest operating system. The guest operating system can be operable to use the address to access the physical device.

Component circuitry for a replaceable printer component, including an address generator which selectively generates component addresses, wherein following an event, the component circuitry performs in succession a plurality of sets of operations, each set of operations including receiving an address change request from a master and changing the component address in response, a last one of the changed component addresses being available as the component address for the component circuitry in one or more subsequent communications with the master.

Embodiments of the present invention provide an apparatus having a plurality of selectable entities having associated physical addresses, wherein the selectable entities are connected to a controller, wherein the selectable entities have a selectable processor configured to determine in response to a common control information a current select information on the basis of selectable logic combinations of a first information describing whether the selectable entity belongs to a first group and a second information describing whether the selectable entity belongs to a second group.