A processor comprises a core, a cache, and a ZCM manager in communication with the core and the cache. In response to an access request from a first software component, wherein the access request involves a memory address within a cache line, the ZCM manager is to (a) compare an OTAG associated with the memory address against a first ITAG for the first software component, (b) if the OTAG matches the first ITAG, complete the access request, and (c) if the OTAG does not match the first ITAG, abort the access request. Also, in response to a send request from the first software component, the ZCM manager is to change the OTAG associated with the memory address to match a second ITAG for a second software component. Other embodiments are described and claimed.

Aspects of the present disclosure relate to data cache management. In embodiments, a storage array's memory is provisioned with cache memory, wherein the cache memory includes one or more sets of distinctly sized cache slots. Additionally, a logical storage volume (LSV) is established with at least one logical block address (LBA) group. Further, at least one of the LSV's LBA groups is associated with two or more distinctly sized cache slots based on an input/output (IO) workload received by the storage array.

Aspects of the present disclosure relate to data cache management. In embodiments, a logical block address (LBA) bucket is established with at least one logical LBA group. Additionally, at least one LBA group is associated with two or more distinctly sized cache slots based on an input/output (IO) workload received by the storage array. Further, the association includes binding the two or more distinctly sized cache slots with at least one LBA group and mapping the bound distinctly sized cache slots in a searchable data structure. Furthermore, the searchable data structure identifies relationships between slot pointers and key metadata.

Solutions for supporting storage using a multi-writer log-structured file system (LFS) are disclosed that include receiving incoming data from an object of a plurality of objects that are configured to simultaneously write to the LFS from different nodes; based at least on receiving the incoming data, determining whether sufficient free segments are available in a local segment usage table (SUT) for writing the incoming data; based at least on determining that insufficient free segments are available, requesting allocation of new free segments; writing the incoming data to a log; acknowledging the writing to the object; determining whether the log has accumulated a full segment of data; based at least on determining that the log has accumulated a full segment of data, writing the full segment of data to a first segment of the free segments; and updating the local SUT to mark the first segment as no longer free.

Solutions for supporting storage using a multi-writer log-structured file system (LFS) are disclosed that include receiving incoming data from an object of a plurality of objects that are configured to simultaneously write to the LFS from different nodes; based at least on receiving the incoming data, determining whether sufficient free segments are available in a local segment usage table (SUT) for writing the incoming data; based at least on determining that insufficient free segments are available, requesting allocation of new free segments; writing the incoming data to a log; acknowledging the writing to the object; determining whether the log has accumulated a full segment of data; based at least on determining that the log has accumulated a full segment of data, writing the full segment of data to a first segment of the free segments; and updating the local SUT to mark the first segment as no longer free.

A system includes a first memory device having a region allocated as a first persistent memory region (PMR) having a first set of pages, a second memory device comprising a non-volatile memory device having a region allocated as a second PMR region having a second set of pages, and at least one processing device, operatively coupled to the first memory device and the second memory device, to implement a PMR mechanism to cause the second PMR region to be accessible through the first PMR region.

A storage device includes a nonvolatile memory device that includes a first area, a second area, and a third area, and a controller that receives a write command and first data from a host device, preferentially writes the first data in the first area or the second area rather than the third area when the first data is associated with a turbo write, and writes the first data in the first area, the second area, or the third area when the first data is associated with a normal write. The controller moves second data between the first area, the second area, and the third area based on the policy received from the host device.

A storage device includes a nonvolatile memory device that includes a first area, a second area, and a third area, and a controller that receives a write command and first data from a host device, preferentially writes the first data in the first area or the second area rather than the third area when the first data is associated with a turbo write, and writes the first data in the first area, the second area, or the third area when the first data is associated with a normal write. The controller moves second data between the first area, the second area, and the third area based on the policy received from the host device.

The present disclosure includes apparatuses and methods for cache operations. An example apparatus includes a memory device including a plurality of subarrays of memory cells, where the plurality of subarrays includes a first subset of the respective plurality of subarrays and a second subset of the respective plurality of subarrays. The memory device includes sensing circuitry coupled to the first subset, the sensing circuitry including a sense amplifier and a compute component. The first subset is configured as a cache to perform operations on data moved from the second subset. The apparatus also includes a cache controller configured to direct a first movement of a data value from a subarray in the second subset to a subarray in the first subset.

The present disclosure includes apparatuses and methods for cache operations. An example apparatus includes a memory device including a plurality of subarrays of memory cells, where the plurality of subarrays includes a first subset of the respective plurality of subarrays and a second subset of the respective plurality of subarrays. The memory device includes sensing circuitry coupled to the first subset, the sensing circuitry including a sense amplifier and a compute component. The first subset is configured as a cache to perform operations on data moved from the second subset. The apparatus also includes a cache controller configured to direct a first movement of a data value from a subarray in the second subset to a subarray in the first subset.