Methods, systems, and devices related to domain-based access in a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). The memory array may be organized according to domains, which may refer to various configurations or collections of access lines, and selections thereof, of different portions of the memory array. In various examples, a memory device may determine a plurality of domains for a received access command, or an order for accessing a plurality of domains for a received access command, or combinations thereof, based on an availability of the signal development cache.

Methods, systems, and devices related to domain-based access in a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). The memory array may be organized according to domains, which may refer to various configurations or collections of access lines, and selections thereof, of different portions of the memory array. In various examples, a memory device may determine a plurality of domains for a received access command, or an order for accessing a plurality of domains for a received access command, or combinations thereof, based on an availability of the signal development cache.

A media management operation is executed to write data from a source block of a cache memory to a set of pages of a destination block of a storage area of a memory sub-system. An entry of a data structure identifying a page count corresponding to the source block of the cache memory is generated. A power loss event associated with the destination block of the storage area is identified. A data recovery operation is executed using the data stored in the source block to complete the write to the destination block. The data is erased from the source block in response to the page count satisfying a condition.

A media management operation is executed to write data from a source block of a cache memory to a set of pages of a destination block of a storage area of a memory sub-system. An entry of a data structure identifying a page count corresponding to the source block of the cache memory is generated. A power loss event associated with the destination block of the storage area is identified. A data recovery operation is executed using the data stored in the source block to complete the write to the destination block. The data is erased from the source block in response to the page count satisfying a condition.

Disclosed herein are an apparatus and method for extracting memory map information from firmware. The apparatus includes one or more processors and executable memory for storing at least one program executed by the one or more processors. The at least one program retrieves memory-related data from firmware, sets a data structure by analyzing binary code based on the memory-related data, and retrieves a memory map structure from the firmware using the data structure.

Disclosed herein are an apparatus and method for extracting memory map information from firmware. The apparatus includes one or more processors and executable memory for storing at least one program executed by the one or more processors. The at least one program retrieves memory-related data from firmware, sets a data structure by analyzing binary code based on the memory-related data, and retrieves a memory map structure from the firmware using the data structure.

Techniques for providing an overlap data buffer to store portions of tiles between passes of chained layers of a neural network are described. One accelerator circuit includes one or more processing units to execute instructions corresponding to the chained layers in multiple passes. In a first pass, the processing unit(s) receives a first input tile of an input feature map from a primary buffer and performs a first operation on the first input tile to obtain a first output tile. The processing unit stores the first output tile in the primary buffer and identifies a portion of the first output tile as corresponding to overlap data between tiles of the input feature map. The processing unit stores the portion in a secondary buffer. In a second pass, the processing unit retrieves the portion to avoid fetching the portion that overlaps and computing the overlap data again.

Provided are a non-volatile dual inline memory module (NVDIMM) supporting a DRAM cache mode and an operation method of the NVDIMM. The NVDIMM includes a DRAM chip, an NVM chip, and a controller that controls the DRAM chip to operate as a cache memory of the NVM chip. The controller sends a read command to the DRAM chip with reference to a cache address of data requested to be written from a host to the NVM chip, and sends a write command to the NVM chip with reference to an address of the data requested to be written at a time point when a read latency (RL) of the DRAM chip and a write latency (WL) of the NVM chip coincide with each other.

Provided are a non-volatile dual inline memory module (NVDIMM) supporting a DRAM cache mode and an operation method of the NVDIMM. The NVDIMM includes a DRAM chip, an NVM chip, and a controller that controls the DRAM chip to operate as a cache memory of the NVM chip. The controller sends a read command to the DRAM chip with reference to a cache address of data requested to be written from a host to the NVM chip, and sends a write command to the NVM chip with reference to an address of the data requested to be written at a time point when a read latency (RL) of the DRAM chip and a write latency (WL) of the NVM chip coincide with each other.

An apparatus is described. The apparatus includes a memory controller to interface with a multi-level memory, where, an upper level of the multi-level memory is to act as a cache for a lower level of the multi-level memory. The memory controller has circuitry to determine: i) an original address of a slot in the upper level of memory from an address of a memory request in a direct mapped fashion; ii) a miss in the cache for the request because the slot is pinned with data from another address that competes with the address; iii) a partner slot of the slot in the cache in response to the miss; iv) whether there is a hit or miss in the partner slot in the cache for the request.