Embodiments of the present disclosure generally relate to a method and device for managing caches. In particular, the method may include in response to receiving a request to write data to the cache, determining the amount of data to be written. The method may further include in response to the amount of the data exceeding a threshold amount, skipping writing data to the cache and writing the data to a lower level storage of the cache. Corresponding systems, apparatus and computer program products are also provided.

A system on chip includes an interconnect circuit having an input interface and a number of output interfaces. A source device is coupled to the input interface. A target device includes a sectorized addressable memory space and a number of access ports respectively coupled to the output interfaces. The source device is configured to deliver a transaction containing an address word to the target device.

A system on chip includes an interconnect circuit having an input interface and a number of output interfaces. A source device is coupled to the input interface. A target device includes a sectorized addressable memory space and a number of access ports respectively coupled to the output interfaces. The source device is configured to deliver a transaction containing an address word to the target device.

The present disclosure relates to computer-implemented systems and methods for locking a region in a cache. In one implementation, a system for locking a cache region may include least one cache configured to store data; at least one register configured to store addresses; and at least one logic circuit configured to perform operations. The operations may include select a portion of the at least one cache for storing one or more lines of data; apply one or more comparator functions to one or more addresses of the selected portion and the stored addresses; and when the one or more addresses of the selected portion and the stored addresses do not overlap, store the one or more lines of data in the selected portion.

A method of operating a cache in a computing device includes, in response to receiving a memory access request at the cache, determining compressibility of data specified by the request, selecting in the cache a destination portion for storing the data based on the compressibility of the data and a persistent fault history of the destination portion, and storing a compressed copy of the data in a non-faulted subportion of the destination portion, wherein the persistent fault history indicates that the non-faulted subportion excludes any persistent faults.

In one example, a system for managing encrypted memory comprises a processor to store a first MAC based on data stored in system memory in response to a write operation to the system memory. The processor can also detect a read operation corresponding to the data stored in the system memory, calculate a second MAC based on the data retrieved from the system memory, determine that the second MAC does not match the first MAC, and recalculate the second MAC with a correction operation, wherein the correction operation comprises an XOR operation based on the data retrieved from the system memory and a replacement value for a device of the system memory. Furthermore, the processor can decrypt the data stored in the system memory in response to detecting the recalculated second MAC matches the first MAC and transmit the decrypted data to cache thereby correcting memory errors.

In one example, a system for managing encrypted memory comprises a processor to store a first MAC based on data stored in system memory in response to a write operation to the system memory. The processor can also detect a read operation corresponding to the data stored in the system memory, calculate a second MAC based on the data retrieved from the system memory, determine that the second MAC does not match the first MAC, and recalculate the second MAC with a correction operation, wherein the correction operation comprises an XOR operation based on the data retrieved from the system memory and a replacement value for a device of the system memory. Furthermore, the processor can decrypt the data stored in the system memory in response to detecting the recalculated second MAC matches the first MAC and transmit the decrypted data to cache thereby correcting memory errors.

In one embodiment, an apparatus includes a memory access circuit to receive memory access instructions and provide at least some of the memory access instructions to a memory subsystem for execution. The memory access circuit may have a conversion circuit to convert the first memory access instruction to a first subline memory access instruction, e.g., based at least in part on an access history for a first memory access instruction. Other embodiments are described and claimed.

A technique for prefetching data for a cache is provided. The technique includes detecting access to a data block. In response to the detection, a prefetch block generates proposed blocks for prefetch. The prefetch block also examines prefetch tracking data to determine whether a prefetch group including the proposed blocks is marked as already having been prefetched. If the group has been marked as already having been prefetched, then then prefetch block does not prefetch that data, thereby avoiding traffic between the prefetch block and the cache memory. Using this technique, unnecessary requests to prefetch data into the cache memory are avoided.

A technique for improving performance of a data compression system is provided. The technique is applicable to compressed data sets that include compression blocks. Each compression block may be either compressed or uncompressed. Metadata indicating whether compression blocks are actually compressed or not is stored. If compression blocks are not compressed, then a read-decompress-modify-compress-write pipeline is bypassed. Instead, a compression unit writes the data specified by the partial request into the compression block, without reading, decompressing, modifying, recompressing, and writing the data, resulting in a much faster operation.