Data exchange between a memory mapped interface and a streaming interface may include receiving sub-packets of a packet from a first interface, storing the sub-packets within a memory at addresses determined according to a ratio of a width of the first interface and a width of a second interface, and determining occupancy, of the memory as the sub-packets are stored. Responsive to determining that the occupancy of the memory meets a trigger level, sub-packets may be read from the memory at addresses determined according to the ratio and sending the sub-packets using the second interface.

There is provided an information transmission apparatus and an information transmission method for suitably transmitting information on power generation or power storage. A unified format of a message is provided to various power generation devices or power storage devices, which may be connected to various apparatuses for outdoor use that cannot use a commercial power supply, such as portable electronic apparatuses, the message transmitting information on a power generation efficiency and other power generation statuses, and the remaining amount, a power storage efficiency, and other power storage statuses of the secondary battery. The electronic apparatus, which uses electric power from the power generation devices or power storage devices, analyzes the message from any of the power generation devices or power storage devices and presents a result to a user.

A system includes a repeater architecture for reads where memory connects to a host for with one bandwidth, and repeats the channel with a lower bandwidth. A memory circuit includes a first group of read signal lines to couple point-to-point between a first group of memory devices and a host device. The memory circuit includes a second, smaller group of read signal lines to couple point-to-point between the first group of memory devices and a second group of memory devices, to extend the memory channel to the second group of memory devices. The memory circuit includes a repeater to share read bandwidth between the first and second groups of memory devices, with up to a portion of the bandwidth for reads to the second group of memory devices, and at least an amount equal to the bandwidth less the portion for reads to the first group of memory devices.

A system with memory includes a repeater architecture where memory connects to a host with one bandwidth, and repeats the channel with a lower bandwidth. A memory circuit includes a first group of signal lines to couple point-to-point between a first group of memory devices and a host device. The memory circuit includes a second group of signal lines to couple point-to-point between the first group of memory devices and a second group of memory devices. The second group of signal lines extends the memory channel to the second group of memory devices. The second group of signal lines includes fewer data signal lines than the first group of signal lines, to support a lower bandwidth than the first group of signal lines on the memory channel.

A controller coupled to a peripheral identifies an access type used by the controller for data transfer. The controller performs operations including: sending information to a peripheral coupled to a controller, the information indicating an access type for which the controller is configured for data transfer; monitoring a communication link with the peripheral for a signal indicating that the peripheral is ready to perform a data transfer according to the access type; and performing, in response to a receipt of the signal through the communication link, the data transfer using data transfer handshake signals that are adapted according to the access type.

A serial interface is provided with a finite state machine configured to compare a current state for a plurality of signals to a previous state to determine whether to transmit a frame including the plurality of signals or to transmit a frame that includes only a bit position of a changed one of the signals.

In accordance with these and other embodiments of the present disclosure, a system may include a plurality of temperature sensors configured to sense temperatures at a plurality of locations associated with an information handling system, a cooling subsystem comprising at least one cooling fan configured to generate a cooling airflow in the information handling system, and a thermal manager communicatively coupled to the plurality of temperature sensors and the cooling subsystem. The thermal manager may be configured to, based on at least a power provided to a subsystem of the information handling system, estimate a thermal condition proximate to the subsystem, based on a maximum power consumption for a component of the subsystem, determine an estimated linear airflow velocity requirement for the component, and set a speed of the at least one cooling fan based on the estimated thermal condition and the estimated linear airflow velocity requirement.

A system may include a plurality of temperature sensors configured to sense temperatures at a plurality of locations associated with an information handling system, a cooling subsystem comprising at least one cooling fan configured to generate a cooling airflow in the information handling system, and a thermal manager communicatively coupled to the plurality of temperature sensors and the cooling subsystem. The thermal manager may be configured to, based on at least a power provided to a subsystem of the information handling system, estimate a thermal condition proximate to the subsystem, correlate each of a plurality of components of the subsystem and a linear airflow velocity requirement of the component to a respective speed of the at least one cooling fan required to provide such airflow requirement, and set a speed of the at least one cooling fan based on the respective speeds.

Disclosed embodiments relate, generally, to interfacing serial communication interfaces of a first device with a parallel communication interface of a second device. A first group of two or more serial communication interfaces and an interfacing logic may be provided. The interfacing logic may form second encoded data blocks by arranging the data elements of the first encoded data blocks such that data elements within a same data element position of respective second encoded data blocks represent a given one of the symbols, and provide the second encoded data blocks to a number of serial communication interfaces coupled to a parallel communication interface of another device. An interfacing logic may additionally or alternatively be configured to receive, from a second group of two or more serial communication interfaces, received encoded data blocks representing received symbols.

A device includes a first component having a data input and a data output. The deice further includes an error correction code (ECC) generation circuit having an input coupled to the data input of the first component. The ECC generation circuit has an output. A second component has a data input coupled to the output of the ECC generation circuit. The second component has a data output. An ECC error detection circuit has a first data input coupled to the data output of the first component, and a second data input coupled to the data output of the second component.