The systems and methods for hang correction in a power management interface bus cause secondary master devices associated with the power management interface bus to utilize timers to determine if a master that won arbitration has asserted a clock signal within a predefined amount of time. If a timer for a secondary master device expires without a clock signal being asserted by the winning master, the secondary master will assume ownership of the bus and assert a clock signal. Priorities between secondary masters are created by using a master identification (MID) value assigned during bus enumeration to determine a timer value. By allowing the secondary masters to assume ownership after expiration of respective timers, bus ownership is maintained in the event that a winning master hangs and does not assert ownership.

A signal processing device is disclosed, which includes a plurality of channel receivers, a plurality of time code processors in one-to-one correspondence with the channel receivers, a timing generator, a signal processor and a transmitter, wherein each channel receiver is configured to parse an audio-video signal which has a data format defined by the SDI protocol and including a time code that characterizes time information. Each time code processor is configured to extract the time code from a parsed audio-video signal obtained by a corresponding channel receiver, and form first frame image data including a frame time code. The signal processor is configured to form an absolute frame output image based on multiple channels of the first frame of image data, frame time codes therein, and an internal clock signal generated by the timing generator. The transmitter is configured to transmit the absolute frame output image for display.

A processor includes a plurality of cores to which individual destination notification dedicated lines are coupled. A destination core selection circuit receives a plurality of packets having some of the cores as destinations, respectively, for arbitration, and selects one first core from among the cores serving as the destinations of the plurality of packets. A data matching circuit compares first transmission data included in a packet for the first core with second transmission data included in a packet for the core other than the first core serving as a destination to participate in the arbitration, extracts one or more second cores of which the second transmission data matches the first transmission data, designates the first core and the second core as the destinations by using the destination notification dedicated lines, and transmits the first transmission data via a data notification line.

Systems, methods, and apparatus provide a multi-master serial peripheral interface. An apparatus is coupled to master and slave devices through an interconnect circuit using individual point-to-point SPI links. The interconnect circuit may be configured to couple pairs of devices selected from the plurality of devices through their individual point-to-point SPI links, enable a first transaction to be completed between a first pair of devices after a first master device in the first pair of devices initiates the first transaction, enable a second transaction to be completed between a second pair of devices after a second master device in the second pair of devices initiates the second transaction, and prevent a collision between the first master device and the second master device while the first pair of devices are engaged in the first transaction. The pairs of devices may be selected when they are participants in one or more transactions.

A bridge for coupling a requesting interconnect and a serving interconnect connected to a number of coherent units in a computer system includes N machines configured to handle requests from the requesting interconnect and for handling allocated responses from the serving interconnect, wherein each of the N machines has an allocated local count; a tracking entity configured to track priorities of the N machines for issuing received requests to the serving interconnect and for issuing received responses to the requesting interconnect based on the N local counts; a first arbiter configured to arbitrate the received requests to be issued to the serving interconnect based on the tracked priorities; and a second arbiter configured to arbitrate the received responses to be issued to the requesting interconnect based on the tracked priorities.

An example integrated circuit (IC) system includes a package substrate having a programmable integrated circuit (IC) and a companion IC mounted thereon, the programmable IC including a programmable fabric and the companion IC including application circuitry. The IC system further includes a system-in-package (SiP) bridge including a first SiP IO circuit disposed in the programmable IC, a second SiP IO circuit disposed in the companion IC, and conductive interconnect on the package substrate electrically coupling the first SiP IO circuit and the second SiP IO circuit. The IC System further includes first aggregation and first dispersal circuits in the programmable IC coupled between the programmable fabric and the first SiP IO circuit. The IC system further includes second aggregation and second dispersal circuits in the companion IC coupled between the application circuitry and the second SiP IO circuit.

A circuit with a first buffer, a second buffer, a third buffer, a fourth buffer, a first data input for first data, a second data input for second data, a data output, and control logic is disclosed. The control logic connects the first data input to one of the buffers, connects the second data input to one of the buffers, and connects the data output to one of the buffers, swap the buffer currently connected to the first data input for a non-connected buffer when first data have been validly written through the first data input into the buffer currently connected to the first data input, swap the buffer currently connected to the second data input for the non-connected buffer when second data have been validly written through the second data input into the buffer currently connected to the second data input.

Implementations of the present disclosure are directed to systems and methods for mapping point-to-point channels to packet virtual channels. A chip with an point-to-point interface converts point-to-point data to a packet format. The point-to-point channels are mapped to virtual channels of the packet transmission protocol. Information from multiple point-to-point channels may be combined in a single packet. Among the benefits of implementations of the present disclosure is that point-to-point devices may be connected to a packetized network without losing the benefits of separate channels for different types of communication. This allows existing point-to-point devices to communicate using a packetized network without internal modification or performance degradation.

A system may include a first device and a second device communicatively coupled to the first device via a communications bus, wherein the communications bus comprises a single clock line for transmission of a clock signal from the first device to the second device, a single frame line for transmission of a frame alignment signal from the first device to the second device, and at least one communications channel for serialized communication of payloads of data between the first device and the second device, wherein the payloads of data have at least two different latencies.

A method for managing frames in a computer providing an operational function and a gateway function between two communication buses in order to transmit messages from a transmitter to a receiver, including: receiving messages from a transmitter via the first bus; storing the received messages; triggering an interrupt of the execution of an operational program causing the processing of the stored messages for transmission to the receiver via the second bus; deactivating the interrupt in order to continue the execution of the functional program, after the expiration of a duration and at the end of the processing of a message currently being processed during the expiration; and, triggering a new interrupt at the end of a timeout of a duration of the execution of the operational program causing the processing of messages stored for transmission to the receiver via the second bus to continue.