A semiconductor package includes multiple dies that share the same package pin. An output enable register provided on each die is used to select the die that drives an output to the shared pin. A hardware arbitration circuit ensures that two or more dies do not drive an output to the shared pin at the same time.

A signal processing device is disclosed, which includes a plurality of channel receivers, a plurality of time code processors in one-to-one correspondence with the channel receivers, a timing generator, a signal processor and a transmitter, wherein each channel receiver is configured to parse an audio-video signal which has a data format defined by the SDI protocol and including a time code that characterizes time information. Each time code processor is configured to extract the time code from a parsed audio-video signal obtained by a corresponding channel receiver, and form first frame image data including a frame time code. The signal processor is configured to form an absolute frame output image based on multiple channels of the first frame of image data, frame time codes therein, and an internal clock signal generated by the timing generator. The transmitter is configured to transmit the absolute frame output image for display.

An interface for an I3C slave. The interface allows I3C slaves to also be connected to a conventional I2C bus that includes an I2C master. For this purpose, an additional adaptation device is provided that adapts the signals of the I2C bus for an I3C slave.

An example integrated circuit (IC) system includes a package substrate having a programmable integrated circuit (IC) and a companion IC mounted thereon, the programmable IC including a programmable fabric and the companion IC including application circuitry. The IC system further includes a system-in-package (SiP) bridge including a first SiP IO circuit disposed in the programmable IC, a second SiP IO circuit disposed in the companion IC, and conductive interconnect on the package substrate electrically coupling the first SiP IO circuit and the second SiP IO circuit. The IC System further includes first aggregation and first dispersal circuits in the programmable IC coupled between the programmable fabric and the first SiP IO circuit. The IC system further includes second aggregation and second dispersal circuits in the companion IC coupled between the application circuitry and the second SiP IO circuit.

An apparatus for a microprocessor computer system and method for configuring the same where said microprocessor computer system comprises a processor core and at least one hardware buffer FIFO with memory-mapped head and tail that handles data movement among the processor cores, networks, raw data input and outputs, and memory. The method for configuring said microprocessor computer system comprises utilizing a FIFO auxiliary processor to process said data traversing said hardware FIFO; utilizing said hardware FIFOs to efficiently pipe data through functional blocks; and utilizing a FIFO controller to perform DMA operations that include non-unit-stride access patterns and transfers among processor cores, networks, raw data input and outputs, memory, and other memory-mapped hardware FIFOs.

Disclosed are a module assembly and a multi-master communication method thereof, and more particularly, a module assembly including a plurality of modules capable of transmitting/receiving data by forming an open drain based one-wire communication bus upon mutual combination, in which at least one module requiring the data transmission among the plurality of modules performs first declaration for a transmission intention by outputting a low signal within a predetermined first arbitration time when at least one module is in an on state by sensing the one-wire communication bus state, at least one module performing the first declaration for the transmission intention performs second declaration for the transmission intention by outputting a high signal within a second arbitration time, and a module which outputs the high signal last within the second arbitration time secures final bus occupation.

A processing and storage circuit includes an internal bus, one or more first-level internal memory units, a central processing unit (CPU), one or more hardware acceleration engines, and an arbiter. The first-level internal memory unit is coupled to the internal bus. The CPU includes a second-level internal memory unit, and is configured to access the first-level internal memory unit via the internal bus, and when the CPU accesses data, the first-level internal memory unit is accessed preferentially. The hardware acceleration engine is configured to access the first-level internal memory unit via the internal bus. The arbiter is coupled to the internal bus, configured to decide whether the CPU or the hardware acceleration engine be allowed to access the first-level internal memory unit. The arbiter sets the priority of the CPU accessing the first-level internal memory unit to be over the hardware acceleration engine.

Systems, methods, and devices can include a first die comprising a first arbitration and multiplexing logic, a first protocol stack associated with a first interconnect protocol, and a second protocol stack associated with a second interconnect protocol. A second die comprising a second arbitration and multiplexing logic. A multilane link connects the first die to the second die. The second arbitration and multiplexing logic can send a request to the first arbitration and multiplexing logic to change a first virtual link state associated with the first protocol stack. The first arbitration and multiplexing logic can receive, from across the multilane link, the request from the first die indicating a request to change the first virtual link state; determine that the first interconnect protocol is ready to change a physical link state; and change the first virtual link state according to the received request while maintaining a second virtual link state.

A method for managing frames in a computer providing an operational function and a gateway function between two communication buses in order to transmit messages from a transmitter to a receiver, including: receiving messages from a transmitter via the first bus; storing the received messages; triggering an interrupt of the execution of an operational program causing the processing of the stored messages for transmission to the receiver via the second bus; deactivating the interrupt in order to continue the execution of the functional program, after the expiration of a duration and at the end of the processing of a message currently being processed during the expiration; and, triggering a new interrupt at the end of a timeout of a duration of the execution of the operational program causing the processing of messages stored for transmission to the receiver via the second bus to continue.

An EtherCAT master-slave station integrated bridge controller, a control method, a control system and a readable storage medium are provided. Therein, an FPGA-based EtherCAT master-slave station integrated bridge controller is constructed. Because of the hardware parallel computing capability of FPGA, the master station of the EtherCAT master-slave station integrated bridge controller has a hard real-time characteristic so as to ensure real-time sending and receiving of EtherCAT network data and reduce the dependence on CPU performance and operating system real-time performance. The EtherCAT master-slave station integrated bridge controller can serve as a slave device relative to a third-party master station device and meanwhile serve as a master device relative to a third-party slave station device, thus reducing the load of EtherCAT bus network and improving the flexibility of network topology.