Disclosed is a method for clock synchronization of an industrial internet field broadband bus, wherein the method is applicable to an industrial internet field broadband bus architecture system including a bus controller and at least one bus terminal, the bus controller is connected with the bus terminal over a two-wire data transfer network, and the method includes steps of: electing one of the bus controller and the bus terminal as a best master clock; determining whether an IP address of the device of the best master clock is the same as an IP address of the bus controller; if so, then determining the bus controller as a master device of clock synchronization, and transmitting by the bus controller a synchronization message to the bus terminal for clock synchronization; and otherwise, returning to the step of electing one of the bus controller and the bus terminal as the best master clock.

A system and method are disclosed for guest-programmable relocation of system tables in a virtualized computer system. In accordance with one embodiment, a hypervisor that is executed by a computer system obtains a first base address of a first portion of memory, where the first base address is in an address space of a guest of a virtual machine, and where the first base address is for a set of one or more system tables that is currently exposed by the hypervisor at a second portion of memory having a second base address in the address space of the guest. The hypervisor then generates a new version of the set of one or more system tables that is exposed to the guest at the first base address.

The present application relates to control systems, clock synchronization methods, controllers, node devices, and vehicles. In one example control system provided in this application, a primary controller directly sends a reference clock signal to at least one node device by using a ring network, and the at least one node device performs timing based on a frequency of the reference clock signal. The reference clock signal is obtained by performing frequency division on a local clock signal of the primary controller.

Systems, methods, apparatuses, and architectures for storage interposers are provided herein. In one example, a storage interposer module includes Peripheral Component Interconnect Express (PCIe) switch circuitry receives storage operations over a host connector that are issued by one or more host systems and transfers the storage operations for storage by one or more storage devices over drive PCIe interfaces. The storage interposer module also includes a control module configured to monitor the storage operations in the PCIe switch circuitry via a control interface coupled between the PCIe switch circuitry and the interposer control module, and selectively direct delivery of each of the storage operations to corresponding storage areas among the one or more storage devices based at least on information monitored about the storage operations in the PCIe switch circuitry.

A path for transmitting encrypted data is completely separated from a path for transmitting unencrypted data. To this end, a virtual secure memory is created on an address space. If a central processing unit (CPU) writes data in the virtual secure memory, hardware stores the data in a specific area of a dynamic random access memory (DRAM) after automatically encrypting the data. In the case where the CPU intents to read data, the hardware sends the data to the CPU after automatically decrypting the data read from a specific area of the DRAM.

A data processing apparatus is provided, that includes communication configured for receiving, from an origin Peripheral Component Interconnect Express (PCIe) device, a translated PCIe packet comprising a destination field that comprises a physical address of a destination PCIe device. Permission circuitry transmits a permission check packet, separate to the translated PCIe packet, to a root port to determine whether the origin PCIe device has permission to access the destination PCIe device. Buffer circuitry stores the translated PCIe packet until a response to the permission check packet is received.

A method of accessing a server address space of a shared PCIe end point system includes programming a primary address translation table with a server address of a server address space, setting up a direct memory access (DMA) to access a primary port memory map, the primary port memory map correlating with addresses in the primary address translation table, and re-directing the direct memory accesses to the primary port memory map to the server address space according to the primary address translation table.

A memory system includes: a plurality of memory devices, one of which includes an unrepaired defective memory cell; a control bus that is shared by the plurality of the memory devices; a plurality of data buses assigned to each of the plurality of the memory devices; and a memory controller that communicates with the plurality of the memory devices through the control bus and the plurality of the data buses, a control latency of the memory device including unrepaired defective memory cells is set differently from a control latency of the other memory devices, where the control latency is used for recognizing control signals of the control bus.

An address translation cache (ATC) is configured to store translation entries indicating mapping information between a virtual address and a physical address of a memory device. The ATC includes a plurality flexible page group caches, a shared cache and a cache manager. Each flexible page group cache stores translation entries corresponding to a page size allocated to the flexible group cache. The shared cache stores, regardless of page sizes, translation entries that are not stored in the plurality of flexible page group caches. The cache manager allocates a page size to each flexible page group cache, manages cache page information on the page sizes allocated to the plurality of flexible page group caches, and controls the plurality of flexible page group caches and the shared cache based on the cache page information.

Methods, systems, and devices for addressing scheme for a memory system are described. A memory system may include a plurality of memory devices that are coupled with various command address (CA) channels via respective pins. In some examples, different pins of each memory device may be coupled with different CA channels. When the memory system receives a command to enter a memory device into a per-device addressability (PDA) mode, certain CA channels may be driven. One or more memory devices may enter the PDA mode based on certain pins of the respective memory device being biased.