G06F13/4045

COMMON-MODE VOLTAGE CONTROL FOR HIGH-SPEED TRANSCEIVERS
20220374061 · 2022-11-24 ·

Circuits and techniques are described for high-speed transceivers (e.g., repeaters such as re-drivers or re-timers) that ensure that the instantaneous voltage at an input or output of a connected device remains within a desired or specified voltage range.

PROCESSING COMPOSITE SIGNALS
20220358068 · 2022-11-10 ·

In some examples, an apparatus for processing a composite signal transmitted uses a first communication protocol via a first port comprising a first connector type, in which the apparatus comprises a processor configured to execute one or more instructions stored in a memory of the apparatus, whereby to cause the apparatus to isolate multiple components of the composite signal received at a first port of the apparatus, the first port of the apparatus, whereby to generate a first and second set of signal components, process at least one component from the second set of signal components to generate a converted signal component, transmit the first set of signal components and the converted signal component from a second port of the apparatus using a second communication protocol, and receive a power supply signal over the second port of the apparatus.

SYSTEMS AND METHODS FOR ENABLING ACCELERATOR-BASED SECURE EXECUTION ZONES
20220358208 · 2022-11-10 ·

The disclosed computer-implemented method may include (1) receiving, by a first internal physical processor of an accelerator from an external processor, a request to access a result of executing a sensitive application within a secure execution zone of the accelerator having (a) a second internal physical processor and (b) physical memory accessible to the second internal physical processor but inaccessible to the first internal physical processor and the external processor, (2) executing, by the second internal physical processor within the secure execution zone, the sensitive application from the physical memory to generate the result, (3) making, by the second internal physical processor, the result accessible outside of the secure execution zone, and (4) relaying, by the first internal physical processor, the result to the external processor. Various other methods, systems, and computer-readable media are also disclosed.

SYSTEM EVENT BROADCAST SYNCHRONIZATION ACROSS HIERARCHICAL INTERFACES

Aspects of the invention include computer-implemented methods, systems, and computer program products that assign a centralized event tag to each communication interface of a plurality of communication interfaces of a chip interconnected in a hierarchy through the communication interfaces to a plurality of chips in a multiprocessing system. A determination is performed of whether to accept or drop a message associated with an event received at one of the communication interfaces of the chip based on comparing a local centralized event tag with a received centralized event tag. The local centralized event tag is updated based on one or more advancing rules to maintain event synchronization between the chip and the plurality of chips.

COMMUNICATION SYSTEM AND LAYOUT METHOD OF COMMUNICATION SYSTEM
20220345134 · 2022-10-27 ·

A communications system includes: a control device; a standard proxy input/output circuit configured to control a standard electric device; and an extension proxy input/output circuit configured to control an extension electric device. The control device and the standard proxy input/output circuit are provided on one substrate, and the control device and the extension proxy input/output circuit are connected to each other via an electric wire.

Power Management Unit

A power management subsystem included in a computer system may include a host device and a power circuit group. The power circuit group includes multiple power circuits arranged in a tree-like structure. The resources of the multiple power circuits are mapped to corresponding addresses within a common address space. The host device sends, via a first communication bus, commands to a branch power circuit of the multiple power circuits, which, in turn, relays the commands, using a second communication bus, to corresponding ones of the other power circuits based on respective power resources specified in the commands received from the host device.

EXPOSING CRYPTOGRAPHIC MEASUREMENTS OF PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIE) DEVICE CONTROLLER FIRMWARE
20230123174 · 2023-04-20 ·

Examples disclosed herein include are computing device hardware components, computing devices, systems, machine-readable mediums, and interconnect protocols that provide for code object measurement of a peripheral device and a method for accessing the measurements to verify integrity across a computing interconnect (e.g., Peripheral Component Interconnect Express - PCIe). For example, a cryptographic processor of a PCIe endpoint (such as a peripheral) may take a measurement (e.g., computing a hash value) of a code object on the device prior to executing the code object. This measurement may be placed in a register that is accessible to another component, such as a host operating system across a PCIe bus for interrogation. The host operating system may utilize an interconnect protocol, such as a PCIe protocol to access the measurement. These measurements may be consumed by a Trusted Platform Manager or other components of a host system that may verify the measurements.

PCIe DEVICE

A peripheral component interconnect express (PCIe) device includes a common function performing operations associated with a PCIe interface according to a function type, the common function being programable to be a function type selected from a plurality function types, an access identification information controller generating first access identification information for allowing an access to the common function, and providing the first access identification information to an assigned system image to which the common function has been assigned, a data packet receiver receiving a data packet including target identification information indicating a target system image from the target system image, and an access allowance determiner determining whether or not to allow the target system image to access the common function based on the first access identification information and the target identification information.

PCIe DEVICE AND OPERATING METHOD THEREOF
20220327081 · 2022-10-13 ·

A Peripheral Component Interconnect Express (PCIe) device performing communication with a host through a PCIe link includes a first physical function, a plurality of second physical functions, and a function mode controller. The first physical function manages the PCIe link and receives function mode control information from the host. Each of the plurality of second physical functions may be enabled or disabled according to a respective operation mode. Based on the function mode control information, the function mode controller sets the operation modes of the plurality of second physical functions to one of an active mode and an inactive mode.

Remotely controlled technician surrogate device

A remote technical support system includes an edge device that operates as a highly secured conduit for a technician to view, access, and control a target device via a secure protocol over a connection medium between the edge device and the target device. The edge device's architecture allows it to selectively present numerous peripheral devices to the target device. The architectural components of the edge device can be controlled by a technician through a secure connection with a trusted server which allows authorized to access the edge device. The edge device also relays technician commands to and obtains diagnostic information from the target device and communicates feedback to the technician over the secure connection. The commands may be relayed to the target via the one or more selectively connected USB peripherals.