An integrated circuit (IC) memory controller is disclosed. The memory controller includes a receiver to receive a strobe signal and provide an internal strobe signal. An adjustable delay circuit delays an enable signal to generate a delayed enable signal. A gate circuit generates a gated strobe signal using the delayed enable signal that masks transitions of the internal strobe signal that occur prior to a valid region of the internal strobe signal. A sample circuit samples data using the gated strobe signal.

A slave node of one or more slave nodes and a master node of a distributed acquisition system and a method of synchronizing communication of the slave node is provided. The method includes acquiring a configuration that provides a definition for a packet interval, wherein the packet interval definition provides an adequate timing margin to ensure that communication packets transmitted by the master node and the one or more slave nodes occur only at harmonics of the packet interval definition. The method further includes receiving master communication packets from the master node via the bus, determining a start time of at least one most recent master communication packet of the master communication packets received from the master node, calculating a synchronization time based on the start time, and starting transmission of slave communication packets to the master node based on the synchronization time.

An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.

A system-on-chip bus system includes a bus configured to connect function blocks of a system-on-chip to each other, and a clock gating unit connected to an interface unit of the bus and configured to basically gate a clock used in the operation of a bus bridge device mounted on the bus according to a state of a transaction detection signal.

A slave node of one or more slave nodes and a master node of a distributed acquisition system and a method of synchronizing communication of the slave node is provided. The method includes acquiring a configuration that provides a definition for a packet interval, wherein the packet interval definition provides an adequate timing margin to ensure that communication packets transmitted by the master node and the one or more slave nodes occur only at harmonics of the packet interval definition. The method further includes receiving master communication packets from the master node via the bus, determining a start time of at least one most recent master communication packet of the master communication packets received from the master node, calculating a synchronization time based on the start time, and starting transmission of slave communication packets to the master node based on the synchronization time.

An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.

A system and apparatus can include a port for transmitting data; and a link coupled to the port. The port can include a physical layer device (PHY) to decode a physical layer packet, the physical layer packet received across the link. The physical layer packet can include a first bit sequence corresponding to a first ordered set, and a second bit sequence corresponding to a second ordered set, the first bit sequence immediately adjacent to the second bit sequence. The first ordered set is received at a predetermined ordered set interval, which can occur following a flow control unit (flit). The first ordered set comprises eight bytes and the second ordered set comprises eight bytes. In embodiments, bit errors in the ordered sets can be determined by checking bits received against expected bits for the ordered set interval.

Disclosed herein are systems and techniques for content protection over synchronous data networks. For example, a method of communicating content protected data may include providing link synchronization information over a link of a synchronous bus, and providing content protected data over the link of the synchronous bus. The content protected data may be protected in accordance with the High-Bandwidth Digital Content Protection (HDCP) specification or the Digital Transmission Content Protection (DTCP) specification, for example.

A distributed network system may include a shared communication bus that operates in accordance with a communication protocol and a plurality of devices coupled to the bus. In accordance with the communication protocol, when one or more of the plurality of devices is actively transmitting data on the bus, each of the plurality of devices receives data via the bus such that bidirectional communication is established among the plurality of devices via the bus, each of the plurality of devices monitors a bus state of the shared communication bus to avoid data contention and to synchronize receipt of encoded symbols and encoded messages comprising encoded symbols via the bus, and each actively transmitting device of the plurality of devices compares the bus state to a desired state of such actively transmitting device to determine a priority among actively transmitting devices of the plurality of devices with respect to the bus.

Port extension apparatus for providing better usage and utilization efficiency ports of end-user devices are disclosed. Port extension apparatus includes at least a main port module for connection to end-user device, first data port module, data transmission control module, second data port module, and video port module. When a to-be-connected device connects to the first data port module, the first data port module and the main port module form a transmission path enabling data transmission between the to-be-connected device and the end-user device. When the to-be-connected device connects to the second data port module, the data transmission control module controls the data transmission between the to-be-connected device and the end-user device. When the to-be-connected device connects to the video port module, the data transmission control module receives the to-be-displayed information from the end-user device and transmits to the to-be-connected device to display.