A data-transmission-format conversion circuit has a first data transmission interface, a second data transmission interface, and a control circuit. The control circuit is coupled to the first data transmission interface and the second data transmission interface for processing data-format conversions between the first data transmission interface and the second data transmission interface. The control circuit is further used to control the second data transmission interface to switch from a first corresponding power mode to a second corresponding power mode when the first data transmission interface is switched from a first power mode to a second power mode. The control circuit is further used to control the second data transmission interface to switch from the first corresponding power mode to a third corresponding power mode when the first data transmission interface is switched from the first power mode to a third power mode.

An integrated circuit (IC) memory controller is disclosed. The memory controller includes a receiver to receive a strobe signal and provide an internal strobe signal. An adjustable delay circuit delays an enable signal to generate a delayed enable signal. A gate circuit generates a gated strobe signal using the delayed enable signal that masks transitions of the internal strobe signal that occur prior to a valid region of the internal strobe signal. A sample circuit samples data using the gated strobe signal.

This application provides a spread spectrum clock negotiation method, and a peripheral component interconnect express device and system, to implement dynamic negotiation between a transmit end and a receive end on an SSC capability in the peripheral component interconnect express system. The method includes: A second PCIe device generates first indication information, where the first indication information is used to indicate whether the second PCIe device has a spread spectrum clock capability. The second PCIe device sends the first indication information to a first PCIe device. The first PCIe device determines, based on the first indication information, whether to perform spread spectrum clock on a reference clock of the first PCIe device.

A method for performing a data transmission between a control device and an electronics unit. A microcontroller and an Ethernet transceiver are provided in the control unit, and a microcontroller and an Ethernet transceiver are also provided in the electronics unit. For data transmission, the two Ethernet transceivers are first synchronized, taking into account a common clock cycle, and, for data transmission, an Ethernet connection is used as a physical route, and the data transmission is carried out with a serial protocol.

An integrated circuit (IC) memory controller is disclosed. The memory controller includes a receiver to receive a strobe signal and provide an internal strobe signal. An adjustable delay circuit delays an enable signal to generate a delayed enable signal. A gate circuit generates a gated strobe signal using the delayed enable signal that masks transitions of the internal strobe signal that occur prior to a valid region of the internal strobe signal. A sample circuit samples data using the gated strobe signal.

A subscriber station for a serial bus system are provided. The subscriber station includes a message creating device for creating a message to be transmitted serially via a bus of the bus system for at least one further subscriber station of the bus system, so that the message has a first time segment and a second time segment, and a transceiver device for serially sending the message to the bus in such a way that data in the first time segment are sent with a slower data rate than in the second time segment, the transceiver device having in the second time segment at least at times an exclusive, collision-free access to the bus, the message creating device to insert an identification number into the first time segment and to begin the second time segment at the latest after the final bit of the identification number and an additional bit.

A retimer apparatus can include a receiver circuit implemented at least partially in hardware; a configuration register comprising a link management bit set, and one or more bit fields for link management bits indicating link management information; bit stream logic implemented at least partially in hardware to encode an ordered set (OS) with one or more link management bits from the configuration register; and a transmitter circuit implemented at least partially in hardware to transmit OS with the one or more link management bits across a link.

In one embodiment, a system includes a peripheral data connection bus configured to connect to devices and transfer data between the devices, a scheduling machine configured to connect to the peripheral data connection bus and send a read request message to a first processing device, and the first processing device configured to be connected to the peripheral data connection bus, and responsively to the read request message add a time value to a read response message, and provide the read response message to the scheduling machine, and wherein the scheduling machine is configured to read the time value from the provided read response message and schedule processing of an operation by a second processing device responsively to the read time value.

An IIC hang link restoration circuit based on a PCA9511A chip, including: a PCA9511A chip, a negation circuit, and an external MOS tube (Q1). An IC bus inside the PCA9511A chip includes a clock line; the PCA9511A chip has one end connected to a master of the IIC bus and the other end connected to a slave of the IIC bus; the PCA9511A chip is provided with input and output interfaces of the clock line, and a ready signal interface; the negation circuit has one end connected to the ready signal interface and the other end connected to a gate electrode of the external MOS tube (Q1), and a source electrode and a drain electrode of the external MOS tube (Q1) are respectively connected to the input interface and the output interface of the clock line of the PCA9511A chip.

An integrated circuit (IC) memory controller is disclosed. The memory controller includes a receiver to receive a strobe signal and provide an internal strobe signal. An adjustable delay circuit delays an enable signal to generate a delayed enable signal. A gate circuit generates a gated strobe signal using the delayed enable signal that masks transitions of the internal strobe signal that occur prior to a valid region of the internal strobe signal. A sample circuit samples data using the gated strobe signal.