The present disclosure relates to asymmetric read/write architectures for enhanced throughput and reduced latency. One example embodiment includes an integrated circuit. The integrated circuit includes a network interface. The integrated circuit also includes a communication bus interface. The integrated circuit is configured to establish a communication link with a processor of the host computing device over the communication bus interface, which includes mapping to memory addresses associated with the processor of the host computing device. The integrated circuit is also configured to receive payload data for transmission over the network interface in response to the processor of the host computing device writing payload data to the mapped memory addresses using one or more programmed input-outputs (PIOs). Further, the integrated circuit is configured to write payload data received over the network interface to the memory of the host computing device using direct memory access (DMA).

An apparatus has a plurality of multi-level comparison circuits, each coupled to a pair of wires in a three-wire communication link, a plurality of first-level clock recovery circuits and a second-level clock recovery circuit. Each multi-level comparison circuit provides a multibit signal as an output. Each first-level clock recovery circuit includes a plurality of first-level flipflops clocked by transitions in a multibit signal received from one multi-level comparison circuit of the plurality of multi-level comparison circuits, and a first delay circuit that delays an output of the each first-level clock recovery circuit to provide a first reset signal that resets the each first-level clock recovery circuit. The second-level clock recovery circuit includes a second-level flipflop clocked by transitions in the outputs of the plurality of first-level clock recovery circuits, and a second delay circuit that delays an output of the second-level clock recovery circuit to provide a second reset signal to the second-level flipflop.

A transceiver for a CAN bus system and a method for detecting a short circuit using a CAN transceiver. The transceiver includes a transmitter for transmitting a transmission signal to a first bus wire of a bus of the bus system, exclusive, collision-free access to the bus of the bus system of a user station being at least temporarily ensured in the bus system, and for transmitting the transmission signal to a second bus wire of the bus, a receiver for receiving the bus signal transmitted on the bus wires, and a diagnostic unit for detecting a short circuit in the bus system, the diagnostic unit being designed to carry out a diagnosis only in a predetermined communication phase of the bus signal.

According to various aspects, a controller may be configured to: control a transmission over a single-wire interface of an instruction corresponding to a high-current operation; and control an electrical behavior of a charging path to provide current at the single-wire interface during a time period corresponding to an execution of the instructed high-current operation.

Disclosed is an RS-485 circuit, which includes an RS-485 interface chip, a start detector, a control module and a counter. The RS-485 interface chip includes a data input terminal and an enable terminal, wherein the data input terminal is configured to receive a data signal, the enable terminal is configured to receive a start signal or a switching signal to make the RS-485 interface chip in a data transmitting state or a data receiving state. The start detector is configured to detect a first signal edge of the data signal to generate the start signal to the enable terminal. After detecting the first signal edge of the data signal, the control module outputs first counting information. The counter is configured to count based on the first counting information, and output the switching signal to the enable terminal when the counter expires.

The invention introduces a method for producing solid state disk (SSD) devices, performed by a processing unit of a production host, to include steps of: loading a port-mapping configuration table including location information regarding each port connected to the production host; comparing location information in a hardware description file with the location information in the port-mapping configuration table to determine which ports that SSD devices are connected to; displaying a graphical user interface (GUI) on a displayer to indicate which ports are connected by SSD devices; and when an SSD device connected to one port that fails to activate, updating the GUI to display information indicating that an SSD device connected to the corresponding port that fails to activate.

In an embodiment a method for operating a processing system includes programming, by a microprocessor during a CAN FD Light data transmission phase, a control register of a Serial Peripheral Interface (SPI) communication interface of the processing system in order to activate a master mode; generating, by the microprocessor during the CAN FD Light data transmission phase, a transmission CAN FD Light frame; storing, by the microprocessor during the CAN FD Light data transmission phase, the transmission CAN FD Light frame to a memory; and activating, by the microprocessor during the CAN FD Light data transmission phase a first DMA channel so that the first DMA channel sequentially transfers the transmission CAN FD Light frame from the memory to a transmission shift register in the SPI communication interface.

A processing system includes a transmission terminal configured to provide a transmission signal, a reception terminal configured to receive a reception signal, a microprocessor programmable via software instructions, a memory controller configured to be connected to a memory, a serial communication interface, and a communication system. Specifically, the serial communication interface supports a CAN FD Light mode of operation and a UART mode of operation. For this purpose, the serial communication interface comprises a control register, a clock management circuit, a transmission shift register, a transmission control circuit, a reception shift register and a reception control circuit. Accordingly, the microprocessor can transmit and/or receive CAN FD Light or UART frames via the same serial communication interface.

There is a problem that video data cannot be relayed from a transmission device having an HDMI connector to a receiving device having a USB Type-C connector. In order to solve the above problem, each of a receiving device having an HDMI reception function unit and a relay device, such as a conversion cable for relaying video data from a transmission device, is made to have a function of determining the other devices. By performing switching of a terminator or a protection element between valid and invalid or performing signal connection switching based on the determination result of the function unit, the above problem can be solved. In addition, it is also possible to realize reverse insertion connection for reversing the video data transmission direction of the relay device.

Systems, apparatuses, and methods for training procedures on reference voltages and sampling times associated with symbols communicated with a memory device are described. The training procedures may be configured to compensate for variations that may occur in different symbols of a signal. For example, an individual training operation may be performed for each reference voltage within a first unit interval. These individual training operations may allow a reference voltage of the first unit interval to be positionable independent of other reference voltages in the same unit interval or in different unit intervals. In another example, an individual training operation may be performed for the sampling time associated with a reference voltage. These individual training operations may allow a sampling time associated with a reference voltage in the first unit interval to be positionable independent of other sampling times in the same unit interval or in different unit intervals.