A port is provided to facilitate a link between a first device and a second device. The port can include a driver circuit to support half duplex communication between the first device and the second device and further include switching logic to receive a value and cause the driver circuit to function in one of a plurality of half duplex modes based on the value. The value is based on a configuration register value corresponding to the port.

A method executable by a low voltage drive circuit (LVDC) includes receiving an analog receive signal, converting the analog receive signal into analog inbound data, converting the analog inbound data into digital inbound data, filtering the digital inbound data to produce filtered digital data, sampling and holding an n-bit digital value of the filtered digital data to produce an n-bit sampled digital data value, adjusting formatting of the n-bit sampled digital data value to produce a formatted digital value, and generating a packet of received digital data from a plurality of formatted digital values.

A system and method for use in dynamic random-access memory (DRAM) comprising entering into a self-refresh mode of operation, exiting the self-refresh mode of operation in response to commands from a self-refresh state machine memory operation (MOP) array, and updating a device state of the DRAM for a target power management state in response to commands from the MOP array.

A bus contention detection circuit includes a delay unit having an input terminal for receiving an output signal of an I/O driver, a duty cycle adjustment unit connected to the delay unit, and a comparison unit having a first input terminal for receiving the output signal, a second terminal for receiving a reference voltage, and an enable terminal for receiving an enable signal of the duty cycle adjustment unit. The enable signal has a rising edge that is delayed relative to a rising edge of the output signal and a falling edge that is aligned with a falling edge of the output signal. The comparison unit compares a voltage level of the output signal with the reference voltage when the enable signal is in a stable voltage state and determine a bus condition in response to a comparison result.

Circuits, methods, and apparatus that may reconstruct a data signal in the presence of ground drift and high-frequency signal coupling. An illustrative embodiment of the present invention may reconstruct a received data signal by taking an finite difference of the received data signal, detecting edges of the received data signal by detecting positive and negative peaks of the finite difference of the received signal, and reconstructing the received data signal using the detected edges. Taking a finite difference of the received data signal removes the DC component of the received data signal, as well as the ground drift that may cause the DC component of the received data signal to change over time. Additional filtering may be used to reduce high-frequency signal coupling and power supply inductive coupling.

An I/O (Input/Output) adapter device can present itself as a network backend driver with an emulated network backend driver interface to a corresponding network frontend driver executing from an operating system running on a host device independent of a virtualization or non-virtualization environment. For each guest operating system executing from its respective virtual machine running on the host device, para-virtualized (PV) frontend drivers can communicate with corresponding PV backend drivers implemented by the I/O adapter device using a corresponding virtual function by utilizing SR-IOV (single root I/O virtualization) functionality.

The present invention discloses a signal output apparatus. Each of two output circuits includes an inverter including an input terminal and an output terminal, and a resistor coupled between the output terminal and a differential output terminal. Each of MOS capacitors is coupled between the output terminals. Under a first operation mode, two current supplying circuits are disabled. The input terminals respectively receive a high and a low state input voltages and the output terminals generate a low and a high state output voltages. The capacitances become larger than a predetermined level. Under a second operation mode, one of the current supplying circuits is enabled to output a supplying current to the differential output terminal. The input terminals receive the high state input voltage. The output terminals generate the low state output voltage. The capacitances become not larger than the predetermined level.

An optical module and a method of transmitting data in the optical module are provided in the present disclosure. According to an example, the optical module may comprise a micro controller unit (MCU) and N number of first driving chips having a same chip address. The MCU may be configured with a serial data (SDA) bus interface and N number of first serial clock (SCL) bus interfaces. Each of the N number of first driving chips may be configured with a SDA bus interface which is configured to be connected with the SDA bus interface on the MCU and a SCL bus interface which is configured to be connected with one of the N number of first SCL bus interfaces on the MCU.

An isolating repeater and corresponding method for Universal Serial Bus (USB) communications. The isolating repeater includes, on either side of a galvanic isolation barrier, front end circuitry coupled to a pair of external terminals, a full speed (FS) transceiver adapted to drive and receive signals over one or more FS isolation channels, and a high speed (HS) transceiver adapted to drive signals over a one HS isolation channel and receive signals over another HS isolation channel. The front end circuitry encodes received signals corresponding to HS data into two-state signals for transmission over one HS isolation channel, and encodes received signals corresponding to HS signaling into two-state signals for transmission over one or more of the FS isolation channels. The front end circuitry on the other side of the isolation barrier decodes the two-state signals received over the one or more FS isolation channels and the two-state signals received over the HS isolation channel for transmission at its external terminals.

A circuit apparatus includes physical layer circuits to which buses compliant with the USB standard are coupled, a processing circuit that performs an FS transfer process, a bus monitoring circuit that monitors the buses, and a bus switching circuit that turns on or off the coupling between a first bus and a second bus based on the result of the monitoring. One of the physical layer circuits includes an FS receiver, an FS driver, and a pull-up control circuit, and the other physical layer circuits includes an FS receiver and an FS driver. When FS_J is detected on the second bus, the bus monitoring circuit turns off the coupling achieved by the bus switching circuit, turns on the pull-up operation performed by the pull-up control circuit, and turns on the FS transfer process performed by the processing circuit.