An optical module configured to control a peer to peer transaction includes a silicon photonics substrate, memory formed on the silicon photonics substrate and configured to store a private key, application circuitry formed on the silicon photonics substrate and coupled to the memory, the application circuitry configured to receive, via an external interface, an electrical signal carrying instructions for executing a transaction, verify the transaction using the private key stored in the memory, and selectively generate a transaction message including information for completing the transaction, and optical communication circuitry formed on the silicon photonics substrate and responsive to the application circuitry, the optical communication circuitry configured to generate an optical signal based on the transaction message and transmit the optical signal to at least one remote entity.

A memory device A memory device can include a serial interface (IF) configured to receive an operational code (op code) of no less than 16-bits and provide a plurality of acknowledgement values in response to the received op code. Controller circuits can generate the plurality of acknowledgement values, including first and second acknowledgement values in response to an operation indicated by the op code being completed, and first and third acknowledgement values in response to an operation indicated by the op code not being completed. Memory circuits can be configured to execute the operation indicated by the op code to access the nonvolatile memory cells, and indicate to the controller circuits whether or not the operation was completed. The first, second and third acknowledgement values can be different multi-bit values. Corresponding methods and systems are also disclosed.

A semiconductor device for determining whether a foreign substance (e.g., water) is present and a method of operating the same are provided. The semiconductor device includes a receptacle including a plurality of pins according to a USB type-C receptacle interface; a first current source providing first current to a CC1 signal pin or a CC2 signal pin among the plurality of pins in a first operation mode; a second current source providing second current to the CC1 signal pin or the CC2 signal pin in a second operation mode; a third current source providing third current to at least two pins of other pins excluding the CC1 signal pin and the CC2 signal pin; and a power delivery integrated circuit (PDIC) controlling the first current source, the second current source and the third current source and detecting the voltage level of a signal outputted to the plurality of pins.

A method for determining a connection status of a device to a cable within a network environment is provided. The method comprises obtaining a signal from a non-data carrying wire of the cable by a detector that is digitally isolated from data transmitted in a data carrying wire of the cable within the network environment, modifying the signal transmitted by the non-data carrying wire to the device and evaluating the modified signal to determine a connection status of the device to the cable.

A circuit apparatus includes physical layer circuits to which buses compliant with the USB standard are coupled, a processing circuit that performs an FS transfer process, a bus monitoring circuit that monitors the buses, and a bus switching circuit that turns on or off the coupling between a first bus and a second bus based on the result of the monitoring. One of the physical layer circuits includes an FS receiver, an FS driver, and a pull-up control circuit, and the other physical layer circuits includes an FS receiver and an FS driver. When FS_J is detected on the second bus, the bus monitoring circuit turns off the coupling achieved by the bus switching circuit, turns on the pull-up operation performed by the pull-up control circuit, and turns on the FS transfer process performed by the processing circuit.

A data processing system includes a main storage, an input/output memory management unit (IOMMU) coupled to the main storage, a peripheral component interconnect (PCI) device coupled to the IOMMU, and a mapper. The system is configured to allocate an amount of physical memory in the main storage and the IOMMU is configured to provide access to the main storage and to map a PCI address from the PCI device to a physical memory address within the main storage. The mapper is configured to perform a mapping between the allocated amount of physical memory of the main storage and a contiguous PCI address space. The IOMMU is further configured to translate PCI addresses of the contiguous PCI address space to the physical memory address within the main storage.

A device includes a first driver circuit coupled to a first bus line, where the first driver circuit includes a first delay element. The first delay element is configured to receive a first input signal and generate a first output signal. The first output signal transitions logic levels after a first delay period when the first input signal transitions from a logic high level to a logic low level. The first output signal transitions logic levels after a second delay period when the first input signal transitions from the logic low level to the logic high level. The first delay element includes a sense amplifier. The first driver circuit is configured to transmit the first output signal over the first bus line. The device also includes a second driver circuit configured to transmit a second output signal over a second bus line.

Methods and apparatus for utilization of preset evaluation to improve input/output performance in high-speed serial interconnects are described. In some embodiments, performance of a link is evaluated at a plurality of equalization values and one of the plurality of equalization values is selected for the link based on comparison of a plurality of margin values that are to be determined for each of the plurality of equalization values. Other embodiments are also claimed and/or disclosed.

Systems, devices, methods, and techniques are disclosed for bus receivers operable to provide a data output corresponding to a voltage differential provided on a two-conductor data bus. In one example, a bus receiver comprises a four-quadrant input circuit and a gain stage coupled to the four-quadrant input circuit. In various examples, the four-quadrant input circuit is operable to provide common mode current compensation based on a common mode voltage present on the two-conductor data bus.

A Power Over Data Lines (PoDL) system includes Power Sourcing Equipment (PSE) supplying DC power and Ethernet data over a single twisted wire pair to a Powered Device (PD). The PSE supplies the DC current and AC data through a cascaded coupling network including a series of AC-blocking inductor stages having different inductances to substantially filter out the AC component and pass the DC component. The data is supplied to the wires via capacitors. The PD may have a matched decoupling network for providing the separated DC power and data to a PD load.