A system and method for use in dynamic random-access memory (DRAM) comprising entering into a self-refresh mode of operation, exiting the self-refresh mode of operation in response to commands from a self-refresh state machine memory operation (MOP) array, and updating a device state of the DRAM for a target power management state in response to commands from the MOP array.

A multi-rank memory bus architecture is provided in which an active DRAM is unterminated and an inactive DRAM terminates to increase the data eye width at the active DRAM.

A value setting associated with one or more parameters of a host-side interface and a memory-side interface of an input/output (I/O) expander is configured to enable Open NAND Flash Interface (ONFI)-compliant communications between a host system and a target memory die of a memory sub-system. The I/O expander processes one or more ONFI-compliant communications between the host system and the target memory die, wherein the one or more ONFI-compliant communications relate to execution of a memory access operation.

The present invention relates to a control system for use in a bus system having at least two transmission lines, having a first control device which has a first termination path and a first terminating resistor connected to the first termination path, a second control device which has a second termination path and a second terminating resistor connected to the second termination path, a first connector which is adapted to connect the first control device to the transmission lines and therefore to integrate the first control device in the bus system, a second connector which is adapted to connect the second control device to the transmission lines and therefore to integrate the second control device in the bus system, wherein the first connector and the second connector are different to one another. The invention also relates to a connector for connecting a control device to transmission lines of a bus system. Finally, the invention also relates to a method for configuring a bus system having at least two transmission lines.

Methods, systems, and devices for multi-level receivers with various operating modes (e.g., on-die termination mode, termination-off mode, etc.) are described. Different modes may be utilized for receiving different types of signaling over a channel. Each mode may correspond to the use of a respective set of receivers configured for the different types of signaling. For example, a device may include a first set of receivers used to receive a first type of signal (e.g., with the channel being actively terminated) and a second set of receivers used to receive a second type of signal (e.g., with the channel being non-terminated). When communicating with another device, based on the type of signaling used for communications, either the first set of receivers or the second set of receivers may be enabled (e.g., through selecting a receiver path for the corresponding mode).

A video transmission system is disclosed. The video transmission system comprises a multi-drop bus, a first source driving chip, a second source driving chip and a timing controller. The first source driving chip comprises a first source driving circuit and a first terminal circuit. The first terminal circuit is coupled to the multi-drop bus and the first source driving circuit for providing a first terminal resistor. The second source driving chip comprises a second source driving circuit and a second terminal circuit. The second terminal circuit is coupled to the multi-drop bus and the second source driving circuit for providing a second terminal resistor. The timing controller is coupled to the first source driving chip and the second source driving chip via the multi-drop bus.

The present technology relates to an electronic device. A storage device in which a memory device controls an ODT operation to improve operation performance of the memory device with a small number of pins includes a plurality of memory devices comprising a target memory device in which an operation is performed and non-target memory devices, and a memory controller configured to control the plurality of memory devices. Each of the plurality of memory devices includes an on die termination (ODT) flag generator configured to generate a flag that indicates that an ODT operation is possible for the non-target memory devices, and an ODT performer configured to determine whether the ODT operation is an ODT read operation for a read operation or an ODT write operation for a write operation based on the flag and configured to generate an enable signal that enables the ODT read operation or the ODT write operation.

A resistance of configurable termination circuitry located at an interface between a memory component and a processing device is adjusted. The configurable termination circuitry includes a plurality of transistors, a plurality of switches coupled to the plurality of transistors, and a plurality of resistors coupled to the plurality of switches. The resistance of the configurable termination circuitry is adjusted based on a mode of the configurable termination circuitry.

A pin-configurable bus termination system may includes a bus connector attached to an end of a bus. The bus connector may be configured for electrically connecting the bus to an input connector of a node. The node may include a bus termination resistance. The bus connector may include a first bus output pin, a second bus output pin and configurable first and second termination resistor pins. The configurable first and second termination resistor pins may be configurable to provide a first termination configuration and a second termination configuration. The first termination configuration may electrically interconnect the first and second bus output pins arid the configurable first and second termination resistor pins to electrically connect the bus termination resistance for terminating the bus. The second termination configuration may include an open electrical circuit between the first and second bus output pins and the configurable first and second termination resistor pins.

Systems, devices, methods, and techniques are disclosed for bus receivers operable to provide a data output corresponding to a voltage differential provided on a two-conductor data bus. In one example, a bus receiver comprises a four-quadrant input circuit and a gain stage coupled to the four-quadrant input circuit. In various examples, the four-quadrant input circuit is operable to provide common mode current compensation based on a common mode voltage present on the two-conductor data bus.