Systems, apparatus and methods are provided for multi-drop multi-load NAND interface topology where a number of NAND flash devices share a common data bus with a NAND controller. A method for controlling on-die termination in a non-volatile storage device may comprise receiving a chip enable signal on a chip enable signal line from a controller, receiving an on-die termination (ODT) command on a data bus from the controller while the chip enable signal is on, decoding the on-die termination command and applying termination resistor (RTT) settings in the ODT command to a selected non-volatile storage unit at the non-volatile storage device to enable ODT for the selected non-volatile storage unit.

Memory devices and a memory controller that controls such memory devices. Multiple memory devices receive commands and addresses on a command/address (C/A) bus that is relayed point-to-point by each memory device. Data is received and sent from these devices to/from a memory controller in a point-to-point configuration by adjusting the width of each individual data bus coupled between the individual memory devices and the memory controller. Along with the C/A bus are clock signals that are regenerated by each memory device and relayed. The memory controller and memory devices may be packaged on a single substrate using package-on-package technology. Using package-on-package technology allows the relayed C/A signals to connect from memory device to memory device using wire bonding. Wirebond connections provide a short, high-performance signaling environment for the chip-to-chip relaying of the C/A signals and clocks from one memory device to the next in the daisy-chain.

Apparatuses and methods associated with voltage tolerant termination presence detection for universal serial bus type-C connectors are disclosed herein. In embodiments, an apparatus to enable voltage tolerant termination presence detection may include sensor circuitry to determine whether a device coupled to the sensor circuitry is to operate in host mode or device mode based on a signal on a configuration channel between the device and the sensor circuitry. In embodiments, the apparatus may further include termination circuitry to bias the configuration channel in accordance with the host mode or the device mode based on the determination of whether the device is to operate in the host mode or the device mode. Other embodiments may be described and/or claimed.

A memory system includes a memory controller and a memory module, where the memory controller is arranged for generating at least a first clock signal and an inverted first clock signal, and the memory module is arranged to receive at least the first clock signal and the inverted first clock signal from the memory controller. In addition, the memory module includes a termination module, and the first clock signal is coupled to the inverted first clock signal through the termination module.

A memory system includes a memory controller and a memory module. The memory controller is arranged for selectively generating at least a clock signal and an inverted clock signal. The memory module includes a first termination resistor, a second termination resistor and a switch module, where a first node of the first termination resistor is to receive the clock signal, a second termination resistor, wherein a first node of the second termination resistor is to receive the inverted clock signal, and the switch module is arranged for selectively connecting or disconnecting a second node of the second termination resistor to a second node of the first termination resistor.

A method of operating a device is disclosed. The method includes attempting communication between the device and a separate connecting device. The attempt utilizes a first resistance and determines whether communication is able to occur at a higher speed mode or lower speed mode. If communication is able to occur at the higher speed mode, using the first resistance, communication continues at the higher speed mode. If communication is not able to occur at the higher speed mode, another attempt through a second resistance is tried. The method again includes determining whether communication is able to occur at the higher speed mode through the second resistance. If communication is able to occur at the higher speed mode through the second resistance, communication continues at the higher speed mode. If communication is not able to occur at the higher speed mode, communication stays at the lower speed mode.

Apparatuses and methods for identifying memory devices of a semiconductor device sharing an external resistance are disclosed. A memory device of a semiconductor device may be set in an identification mode and provide an identification request to other memory devices that are coupled to a common communication channel. The memory devices that are coupled to the common communication channel may share an external resistance, for example, for calibration of respective programmable termination components of the memory devices. The memory devices that receive the identification request set a respective identification flag which can be read to determine which memory devices share an external resistance with the memory device having the set identification mode.

The present disclosure relates to the field of optical communications. A board is disclosed. The board includes a level adjustment circuit, a detection apparatus, and a control apparatus. The detection apparatus is configured to: when the detection apparatus is connected to an optical module, receive an indication signal output by an upstream optical signal detection pin; continuously detect a received first level signal and the received indication signal. If there is a second level signal, opposite to the first level signal, the detection apparatus notifies the control apparatus that the optical module is inserted. If there is no second level signal in the signal received within the preset duration, the detection apparatus notifies the control apparatus that the optical module is absent. This makes the optical module less dependent on the in-position pin, and decreases a quantity of pins of the optical module.

A termination for a high-frequency transmission line includes a first resistor that has a first terminal coupled to a first end of a transmission line and a second terminal coupled to a first input/output pad, and a second resistor that has a first terminal coupled to the first input/output pad. The first resistor and the second resistor may provide a combined resistance that matches a nominal value of a characteristic impedance of the transmission line. The apparatus may include a third resistor having a first terminal coupled to a second end of a transmission line, and a second terminal coupled to a second input/output pad, and a fourth resistor having a first terminal coupled to the second input/output pad. The third resistor and the fourth resistor may provide a combined resistance that matches the nominal value of the characteristic impedance of the transmission line.

The present disclosure is directed to an input/output module. In some embodiments, the input/output module includes: a plurality of communication channels, each channel of the plurality of communication channels configured to connect to one or more field devices; switch fabric configured to selectively facilitate connectivity between an external control module and the one or more field devices via the plurality of communication channels; a serial communications port configured for connecting the input/output module to the control module in parallel with a second input/output module, the serial communications port configured for transmitting information between the input/output module and the control module; and a parallel communications port configured for separately connecting the input/output module to the control module, the parallel communications port configured for transmitting information between the input/output module and the control module, and transmitting information between the input/output module and the second input/output module.