Representative apparatus, method, and system embodiments are disclosed for configurable computing. A representative system includes an interconnection network; a processor; and a plurality of configurable circuit clusters. Each configurable circuit cluster includes a plurality of configurable circuits arranged in an array; a synchronous network coupled to each configurable circuit of the array; and an asynchronous packet network coupled to each configurable circuit of the array. A representative configurable circuit includes a configurable computation circuit and a configuration memory having a first, instruction memory storing a plurality of data path configuration instructions to configure a data path of the configurable computation circuit; and a second, instruction and instruction index memory storing a plurality of spoke instructions and data path configuration instruction indices for selection of a master synchronous input, a current data path configuration instruction, and a next data path configuration instruction for a next configurable computation circuit.

A data transmission medium includes first and second conductors and a first reversible plug connector coupled to a first end thereof. The first reversible plug connector includes a plurality of signal pins, a crossbar switch, a receiver, and a transmitter. In response to a first configuration state, the plurality of signal pins includes a first predetermined number of reception pins and a second predetermined number of transmission pins. The first and second predetermined numbers are different from each other and each is greater than zero. The crossbar switch couples the first predetermined number of reception pins to a first port and the second predetermined number of transmission pins to a second port. The receiver has an input coupled to the first conductor, and an output coupled to the first port. The transmitter has an input coupled to the second port and an output coupled to the second conductor.

A communicating entities include one master entity, configured for communicating according to a first protocol at least, and a plurality of slave entities. The slave entities include a first group of slave entities able to support communications according to said first protocol and unable to support communications according to a second protocol, and a second group of slave entities able to support communications according to at least said second protocol. The first protocol is implemented by a token passing with communication data from the master entity to successively each neighbour slave entity, until the token reaches again the master entity, defining thus a first cycle according to the first protocol. The second protocol is implemented by passing a data frame including data intended to entities of said second group, one current entity of said second group, when receiving said data frame.

An example computing system includes a baseboard management controller (BMC), a motherboard, and a daughterboard communicatively coupled to the motherboard. The BMC includes a serial interface. The daughterboard includes a universal asynchronous receiver/transmitter (UART) terminal, a bridging chip, and a microcontroller communicatively coupled to the BMC via the bridging chip. The BMC establishes a serial connection, through the serial interface and the UART terminal, with the microcontroller.

A data processing system includes multiple powered domains which communicate using a bridge 10. The bridge 10 includes first bridge circuitry 14 within a first power domain and second bridge circuitry 16 within a second power domain. The first bridge circuitry 14 and the second bridge circuitry 16 exchange intra-bridge power control signals which serve to control management of the communication channel through the bridge 10 to adopt a communication open state or a communication quiesced state independent of whether either side of the bridge is in a power-active state or a power-inactive state.

A data transmission medium includes first and second conductors and a first reversible plug connector coupled to a first end thereof. The first reversible plug connector includes a plurality of signal pins, a crossbar switch, a receiver, and a transmitter. In response to a first configuration state, the plurality of signal pins includes a first predetermined number of reception pins and a second predetermined number of transmission pins. The first and second predetermined numbers are different from each other and each is greater than zero. The crossbar switch couples the first predetermined number of reception pins to a first port and the second predetermined number of transmission pins to a second port. The receiver has an input coupled to the first conductor, and an output coupled to the first port. The transmitter has an input coupled to the second port and an output coupled to the second conductor.

An example computing system includes a baseboard management controller (BMC), a motherboard, and a daughterboard communicatively coupled to the motherboard. The BMC includes a serial interface. The daughterboard includes a universal asynchronous receiver/transmitter (UART) terminal, a bridging chip, and a microcontroller communicatively coupled to the BMC via the bridging chip. The BMC establishes a serial connection, through the serial interface and the UART terminal, with the microcontroller.

A method for stack timing adjustment for serial communications is provided. The method includes receiving a USB communication, decoding the USB communication into UART frames, and adjusting the timing of the UART frames according to a serial protocol.

A method for the transmission of data via an Inter Communication Link (ICL) to a receiver unit is provided. The method identifies data to be transmitted in a memory cell of a data storage. The method continues by extracting the address of the memory cell and extracting the data word from the identified data. The method continues by calculating a CRC (cyclic redundancy check) checksum from the extracted address of the memory cell and the extracted data word. The method continues by generating a data packet to be sent by appending a start frame delimiter and a stop frame delimiter to the extracted address of the memory cell, the extracted data word and the calculated CRC checksum. The method continues by sending the data packet.

This disclosure relates to methods, non-transitory computer readable media, and systems that asynchronously train a machine learning model across client devices that implement local versions of the model while preserving client data privacy. To train the model across devices, in some embodiments, the disclosed systems send global parameters for a global machine learning model from a server device to client devices. A subset of the client devices uses local machine learning models corresponding to the global model and client training data to modify the global parameters. Based on those modifications, the subset of client devices sends modified parameter indicators to the server device for the server device to use in adjusting the global parameters. By utilizing the modified parameter indicators (and not client training data), in certain implementations, the disclosed systems accurately train a machine learning model without exposing training data from the client device.