A subscriber station for a serial bus system are provided. The subscriber station includes a message creating device for creating a message to be transmitted serially via a bus of the bus system for at least one further subscriber station of the bus system, so that the message has a first time segment and a second time segment, and a transceiver device for serially sending the message to the bus in such a way that data in the first time segment are sent with a slower data rate than in the second time segment, the transceiver device having in the second time segment at least at times an exclusive, collision-free access to the bus, the message creating device to insert an identification number into the first time segment and to begin the second time segment at the latest after the final bit of the identification number and an additional bit.

A method of improving synchronization over a secure digital (SD) bus between an SD host and an SD client device is described. The method includes writing to a client event register to interrupt the SD host for an SD extended command. The method also includes triggering the SD host to issue the SD extended command to the SD client device over the SD bus in response to the SD client device writing to the client event register.

A communications control system is disclosed that includes a serial communications interface and a parallel communications interface for coupling a plurality of input/output modules with a control module. The serial communications interface is configured for connecting the plurality of input/output modules to the control module in parallel to transmit information between the plurality of input/output modules and the control module, and the parallel communications interface is configured for separately connecting the plurality of input/output modules to the control module to transmit information between the plurality of input/output modules and the control module, and to transmit information between individual ones of the plurality of input/output modules. The serial communications interface may comprise a multidrop bus, and the parallel communications interface may comprise a cross switch.

Dynamic bus inversion (DBI) for programmable levels of a ratio of ones and zeros. A transmitting device identifies a number and/or ratio of ones and zeros in a noninverted version of a signal to be transmitted (noninverted signal) and a number and/or ratio of ones and zeros in an inverted version of the signal (inverted signal). The transmitting device can calculate whether a difference of ones and zeros in the noninverted signal or a difference of ones and zeros in the inverted signal provides a calculated average ratio of ones to zeros closer to a target ratio. The transmitting device sends the signal that achieves provides the calculated average ratio closer to the target ratio.

Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.

An apparatus includes a first device having a clock signal and configured to communicate, via a data bus, with a second device configured to assert a data strobe signal and a plurality of data bit signals on the data bus. The first device may include a control circuit configured, during a training phase, to determine relative timing between the clock signal, the plurality of data bit signals, and the data strobe signal. The first device may determine, using a first set of sampling operations, a first timing relationship of the plurality of data bit signals relative to the data strobe signal, and determine, using a second set of sampling operations, a second timing relationship of the plurality of data bit signals and the data strobe signal relative to the clock signal. During an operational phase, the control circuit may be configured to use delays based on the first and second timing relationships to sample data from the second device on the data bus.

A cycle control circuit may include a judgement pulse generation circuit, a detection signal generation circuit or a flag generation circuit. The judgement pulse generation circuit may be configured to set a predetermined value based on an initialization signal and a period signal, and to generate a judgment pulse. The detection signal generation circuit may be configured to generate a detection signal from a reference flag. The flag generation circuit may be configured to generate a reference flag based on a reference signal. A cycle of the reference signal may be maintained or adjusted based on the reference flag.

Disclosed is a mechanism maintain flow rate limits to flows in a server operating in a single root input/output virtualization (SR-IOV) environment. A transmit pipeline assigns a dedicated transmit queue to a flow. A scheduler allocates a flow transmit bandwidth to the dedicated transmit queue to enforce the flow rate limit. The transmit pipeline assigns the dedicated transmit queue to the flow upon receiving a packet of the flow. A queue identifier (ID) for the dedicated transmit queue is forwarded to a tenant process acting as a source of the flow to support forwarding of packets of the flow to the proper transmit queue. The transmit pipeline maintains security by comparing packet destinations of packets with the destination of the flow associated with the dedicated transmit queue. Packets in the dedicated destination queue with destinations that do not match the flow destination may be dropped.

A data transmission circuit includes a data bus inversion encoding circuit configured to compare previous output data and current output data, invert or non-invert the current output data to control the number of data transitions; and transmitters configured to drive signal transmission lines based on outputs of the data bus inversion encoding circuit.

Embodiments are directed to a bus bridge transfer protocol in a bus bridge system that uses a tag based transfer protocol to identify transactions. The bus bridge may receive a protocol request from an initiator that does not use the tag based transfer protocol. A designated tag consistent with the tag based transfer protocol may be assigned for use in requests from the non-tag conforming initiator. When receiving a request from the non-tag conforming initiator, an initiator flag is set to indicate that the request is from the non-tag conforming initiator and that the response should be forwarded to the non-tag conforming initiator. When receiving a request from a tag conforming initiator, if the request includes the designated tag, the initiator flag is set to indicate that the response should be forwarded to and that the designated tag is being used in a request from the tag conforming initiator.