A data processing network and method of operation thereof are provided for efficient transfer of ordered data from a Request Node to a target node. The Request Node send write requests to a Home Node and the Home Node responds to a first write request when resources have been allocated the Home Node. The Request Node then sends the data to the written. The Home Node also responds with a completion message when a coherency action has been performed at the Home Node. The Request Node acknowledges receipt of the completion message with a completion acknowledgement message that is not sent until completion messages have been received for all write requests older than the first write request for the ordered data, thereby maintaining data order. Following receipt of the completion acknowledgement for the first write request, the Home Node sends the data to be written to the target node.

Dynamic bus inversion (DBI) for programmable levels of a ratio of ones and zeros. A transmitting device identifies a number and/or ratio of ones and zeros in a noninverted version of a signal to be transmitted (noninverted signal) and a number and/or ratio of ones and zeros in an inverted version of the signal (inverted signal). The transmitting device can calculate whether a difference of ones and zeros in the noninverted signal or a difference of ones and zeros in the inverted signal provides a calculated average ratio of ones to zeros closer to a target ratio. The transmitting device sends the signal that achieves provides the calculated average ratio closer to the target ratio.

Representative apparatus, method, and system embodiments are disclosed for configurable computing. A representative system includes an interconnection network; a processor; and a plurality of configurable circuit clusters. Each configurable circuit cluster includes a plurality of configurable circuits arranged in an array; a synchronous network coupled to each configurable circuit of the array; and an asynchronous packet network coupled to each configurable circuit of the array. A representative configurable circuit includes a configurable computation circuit and a configuration memory having a first, instruction memory storing a plurality of data path configuration instructions to configure a data path of the configurable computation circuit; and a second, instruction and instruction index memory storing a plurality of spoke instructions and data path configuration instruction indices for selection of a master synchronous input, a current data path configuration instruction, and a next data path configuration instruction for a next configurable computation circuit.

Apparatuses and methods for controlling access to a common bus including a plurality of memory devices coupled to a common bus, wherein individual ones of the plurality of memory devices are configured to access the common bus responsive to a strobe signal, and a strobe line driver programmed with a first delay associated with a combination of a first command type and a first one of the plurality of memory devices to provide a first strobe signal to the first one of the plurality of memory devices, and further programmed with a second delay associated with a combination of a second command type and a second one of the plurality of memory devices to provide a second strobe signal to the second one of the plurality of memory devices.

A synchronous transmission device includes a first communication port, a first bus instance and a second bus instance. The first communication port is connected to the first endpoint and the second endpoint. The first bus instance executes a first data transmission with the first endpoint according to a first node of a first schedule list. The first node corresponds to the first endpoint, and the first bus instance corresponds to the first communication port. When the first data transmission is executed, the first bus instance is further configured to determine whether the second bus instance is idle. When the second bus instance is idle, the first bus instance controls the second bus instance to execute a second data transmission with the second endpoint according to a second node of the first schedule list. The second node of the first schedule list corresponds to the second endpoint.

A subscriber station for a serial bus system are provided. The subscriber station includes a message creating device for creating a message to be transmitted serially via a bus of the bus system for at least one further subscriber station of the bus system, so that the message has a first time segment and a second time segment, and a transceiver device for serially sending the message to the bus in such a way that data in the first time segment are sent with a slower data rate than in the second time segment, the transceiver device having in the second time segment at least at times an exclusive, collision-free access to the bus, the message creating device to insert an identification number into the first time segment and to begin the second time segment at the latest after the final bit of the identification number and an additional bit.

Dynamic bus inversion (DBI) for programmable levels of a ratio of ones and zeros. A transmitting device identifies a number and/or ratio of ones and zeros in a noninverted version of a signal to be transmitted (noninverted signal) and a number and/or ratio of ones and zeros in an inverted version of the signal (inverted signal). The transmitting device can calculate whether a difference of ones and zeros in the noninverted signal or a difference of ones and zeros in the inverted signal provides a calculated average ratio of ones to zeros closer to a target ratio. The transmitting device sends the signal that achieves provides the calculated average ratio closer to the target ratio.

A data transmission circuit includes a data bus inversion encoding circuit configured to compare previous output data and current output data, invert or non-invert the current output data to control the number of data transitions; and transmitters configured to drive signal transmission lines based on outputs of the data bus inversion encoding circuit.

A cycle control circuit may include a judgement pulse generation circuit, a detection signal generation circuit or a flag generation circuit. The judgement pulse generation circuit may be configured to set a predetermined value based on an initialization signal and a period signal, and to generate a judgment pulse. The detection signal generation circuit may be configured to generate a detection signal from a reference flag. The flag generation circuit may be configured to generate a reference flag based on a reference signal. A cycle of the reference signal may be maintained or adjusted based on the reference flag.

A system interconnect is provided which includes a first channel configured to transmit a plurality of control signals based on a first clock, and a second channel configured to transmit a plurality of data signals which correspond to the control signals based on a second clock. The first channel and the second channel allows a predetermined range of out-of-orderness, and the predetermined range of the out-of-orderness indicates that an order of the control signals is different from an order of the data signals which correspond to the control signals.