Sending and/or receiving messages in a computer system having memory and a processor. The method includes configuring the memory to have one or more streams connecting a generic messaging client to send messages to and/or receive messages from one or more protocol-specific messaging clients. The streams are formed by providing configuration data comprising one or more destination definitions. Each of the destination definitions corresponds to one of the protocol-specific messaging clients. Each of the destination definitions has a specified messaging protocol and one or more stream definitions. Each of the stream definitions has parameters associated with the specified messaging protocol of a corresponding one of the destination definitions. In code for the generic messaging client, at least one stream object is provided specifying one of the destination definitions and one of the stream definitions.

A method for synchronizing transactions between components of a system on chip includes monitoring a partial sequence of transactions that use AXI communication protocol for a stream of address calls and a streams of transfer batches. For each of the address calls and transfer batches identified by the same unique identifier, extracting an anticipated an anticipated number of transfers per batch from each of the address calls of the stream of address calls, and recursively, comparing the anticipated numbers of transfers extracted from the address calls of the stream of address calls with the number of transfers in the transfer batches of the stream of batches. Pairing a predetermined number of consecutive address calls of the stream of address calls with consecutive batches of the stream of batches based on the comparison.

A method for managing communications involving a lockstep processing comprising at least a first processor and a second processor can include receiving, at a data synchronizer, a first signal from a first device. The method can also include receiving, at the data synchronizer, a second signal from a second device. In addition, the method can include determining, by the data synchronizer, whether the first signal is equal to the second signal. When the first signal is equal to the second signal, the method can include transmitting, by the data synchronizer, the first signal to the first processor and the second signal to the second processor. Specifically, in example embodiments, transmitting the first signal to the first processor can occur synchronously with transmitting the second signal to the second processor.

An apparatus is provided that compensates for misalignment on a synchronous data bus, the apparatus includes a replica radial distribution element, a bit lag control element, and a synchronous lag receiver. The replica radial distribution element is configured to receive a lag pulse signal, and is configured to generate a replicated strobe signal, where the replica radial distribution network includes replicated propagation path lengths, loads, and buffering of a radial distribution network for a strobe. The bit lag control element is configured to measure the time between assertion of the lag pulse signal and assertion of the replicated strobe signal, and is configured to generate a first value on a lag bus that indicates the time. The bit lag control element has delay lock control that is configured to select one of a plurality of successively delayed versions of the lag pulse signal that coincides with the assertion the replicated strobe signal, and is configured to generate a second value on a lag select bus that indicates the propagation time, where the delay lock control selects the one of a plurality of successively delayed versions of the lag pulse signal by incrementing and decrementing bus states of select inputs on a mux, and where the plurality of successively delayed versions comprises inputs to the mux, and where the plurality of successively delayed versions comprises outputs a first plurality of series-coupled matched inverter pairs. The synchronous lag receiver is coupled to the bit lag control element, and is configured to receive a first one of a plurality of radially distributed strobes and a data bit, and is configured to delay registering of the data bit by the time.

An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a replica radial distribution element, a Joint Test Action Group (JTAG) interface, and a bit lag control element. The replica radial distribution element is configured to receive a lag pulse signal, and is configured to generate a replicated strobe signal, where the replica radial distribution network includes replicated propagation path lengths, loads, and buffering of a radial distribution network for a strobe. The JTAG interface is configured to receive control information over a standard JTAG bus, where the control information indicates an amount to adjust a propagation time. The bit lag control element is configured to measure, when an update signal is asserted, the propagation time beginning with assertion of the first signal and ending with assertion of the second signal, and is configured to generate a first value on a lag bus that indicates an adjusted propagation time. The bit lag control element includes delay lock control, adjust logic, and a gray encoder. The delay lock control is configured to select one of a plurality of successively delayed versions of the first signal that coincides with the assertion the second signal, and is configured to generate a second value on a lag select bus that indicates the propagation time, where the delay lock control selects the one of a plurality of successively delayed versions of the first signal by incrementing and decrementing bus states of select inputs on a mux, and where the plurality of successively delayed versions includes inputs to the mux, and where the plurality of successively delayed versions includes outputs a first plurality of series-coupled matched inverter pairs. The adjust logic is coupled to the JTAG interface and to the lag select bus, and is configured adjust the second value by the amount prescribed by the JTAG interface to yield a third value that is output to an adjusted lag bus. The gray encoder is configured to gray encode the third value to generate the first value on the lag bus.

Disclosed is a mechanism maintain flow rate limits to flows in a server operating in a single root input/output virtualization (SR-IOV) environment. A transmit pipeline assigns a dedicated transmit queue to a flow. A scheduler allocates a flow transmit bandwidth to the dedicated transmit queue to enforce the flow rate limit. The transmit pipeline assigns the dedicated transmit queue to the flow upon receiving a packet of the flow. A queue identifier (ID) for the dedicated transmit queue is forwarded to a tenant process acting as a source of the flow to support forwarding of packets of the flow to the proper transmit queue. The transmit pipeline maintains security by comparing packet destinations of packets with the destination of the flow associated with the dedicated transmit queue. Packets in the dedicated destination queue with destinations that do not match the flow destination may be dropped.

Disclosed is a semiconductor device including: a bus; a slave function block coupled to the bus; a master function block coupled to the bus through a bus interface, and suitable for providing a bus ID to the slave function block together with a request when transmitting the request to the slave function block; and a subordinate slave function block suitable for monitor the bus interface. The subordinate slave function block catches the data communicated together with the bus ID is matched to any one of a plurality of determined bus IDs.

A master for transmitting data to a slave via a bus segment by segment is provided. The master includes a finite state machine (FSM) configured to receive and analyze dirty bits for first data segments to be included in a current segment among the data and to output a first selection signal and location information related to the current segment according to an analysis result and a first multiplexer configured to determine whether to output the current segment as a dirty data segment to the bus based on the first selection signal.

Physical layer logic is provided that is to receive data on one or more data lanes of a physical link, receive a valid signal on another of the lanes of the physical link identifying that valid data is to follow assertion of the valid signal on the one or more data lanes, and receive a stream signal on another of the lanes of the physical link identifying a type of the data on the one or more data lanes.

A communications control system is disclosed that includes a serial communications interface and a parallel communications interface for coupling a plurality of input/output modules with a control module. The serial communications interface is configured for connecting the plurality of input/output modules to the control module in parallel to transmit information between the plurality of input/output modules and the control module, and the parallel communications interface is configured for separately connecting the plurality of input/output modules to the control module to transmit information between the plurality of input/output modules and the control module, and to transmit information between individual ones of the plurality of input/output modules. The serial communications interface may comprise a multidrop bus, and the parallel communications interface may comprise a cross switch.