A port of a computing device includes protocol circuitry to implement a particular interconnect protocol, where the protocol circuitry is to generate a set of ordered sets defined according to the particular interconnect protocol. The set of ordered sets is generated for a link to couple a first device to a second device and the set of ordered sets comprises link information for the link. Translation layer circuitry is provided to: generate, from the set of ordered sets, at least one data structure to comprise at least a portion of the link information, and cause the data structure to be sent from the first device to the second device on the link in lieu of the set of ordered sets.

An industrial control system, such as a process control for use in a process plant, uses a hardware/software architecture that makes the system more reactive by making the system more resilient, responsive, and elastic. The industrial control system includes one or more distributed input/output (I/O) controller devices (BFN I/O controllers) which are coupled to field devices within a plant and provide direct or indirect access to the field devices for control and messaging purposes, one or more advanced function and computation nodes, and one or more user nodes coupled to the BFN I/O controllers via a network connection. The advanced function nodes store and execute virtual machines, devices, or entities, which decouples the hardware used in the control system from the software that functions on that hardware, making the system easier to scale, reconfigure, and change. Moreover, the industrial control system uses a self-describing data messaging scheme that provides both the data and a description of the data from a sender to a receiver, which enables different messaging protocols and data formats to be used in the control system, which also makes the system more open.

An example programmable integrated circuit (IC) includes a processor, a plurality of endpoint circuits, a network-on-chip (NoC) having NoC master units (NMUs), NoC slave units (NSUs), NoC programmable switches (NPSs), a plurality of registers, and a NoC programming interface (NPI). The processor is coupled to the NPI and is configured to program the NPSs by loading an image to the registers through the NPI for providing physical channels between NMUs to the NSUs and providing data paths between the plurality of endpoint circuits.

Methods and systems for facilitating an equitable bandwidth distribution across downstream devices in asymmetrical switch topologies, and in particular asymmetrical PCIe switch topologies. The equitable distribution of bandwidth is achieved in asymmetrical topologies using virtual switch partitioning. An upstream switch that is connected to the root complex via an upstream port and that receives bandwidth B from the upstream port, is virtualized into two or more virtual switches. Each virtual switch equally shares the bandwidth. Each virtual switch is allocated to downstream devices that are connected to the upstream switch as well as to one or more downstream switches that are connected to the upstream switch. Each downstream switch may be connected to one or more additional downstream devices.

A computer-implemented method manages I/O queues in a host clustered system. The method includes, receiving, from a first virtual machine (VM), a request to establish a set of I/O queues in a storage system, and the first VM is supported by a first host. The method further includes, mapping a data volume to a target storage system, wherein the data volume is related to the request. The method includes, sending a first connection request from the first host to the target storage system. The method further includes, establishing, in response to the first connection request, a connection between the first host and the target storage system. The method incudes, blocking a second connection request, wherein the second connection request is directed to a second storage system, the second storage system being included in the storage system.

Method for digital, bidirectional data transmission between a position measuring system (3-7) and a motor control device (1) and/or an evaluation unit based on the transmission of frames (34, 35, 36) of a predefined bit length in chronologically sequential time slots (28-30), wherein a primary master (1) communicates via a two wire bus line (2) with the position measuring system (3-7) and/or the motor unit (11, 14) and/or the evaluation unit with a primary slave (3) disposed there, and that additional sub-slaves (12, 15) can be coupled in parallel to the primary slave (3), which sub-slaves communicate on the same bus line (2), which the primary master (1) uses with the primary slave (3).

An encapsulation block for a digital signal processing (DSP) block. The encapsulation block includes DSP block having an input terminal, an output terminal, and an input clock. The encapsulation block also includes pacing control network operatively connected with the input terminal, the output terminal, and the input clock of the DSP block. The input terminal of the DSP block is configured to receive a samples-in data stream inputted at a predefined clock period defined by the input clock. The output terminal of the DSP block is configured to receive a samples-out data stream outputted at a predefined paced parameter. The pacing control network is configured to control data flow at the samples-in data stream and the samples-out data stream independently of the DSP block.

Representative apparatus, method, and system embodiments are disclosed for configurable computing. A representative system includes an asynchronous packet network; a plurality of configurable circuits arranged in an array, each configurable circuit coupled to the asynchronous packet network and adapted to perform a plurality of computations; and a dispatch interface circuit adapted to partition the plurality of configurable circuits into one or more separate partitions of configurable circuits and to load one or more computation kernels into each partition of configurable circuits. The dispatch interface circuit may load balance across the partitions of configurable circuits by starting threads for execution in the partition having the highest number of available thread identifiers. The dispatch interface may also assert a partition enable signal to merge the one or more separate partitions and assert a stop signal to all configurable circuits of the one or more separate partitions of configurable circuits.

An adapter is provided that includes a first interface to couple to a particular device, where link layer data is to be communicated over the first interface, and a second interface to couple to a physical layer (PHY) device. The PHY device includes wires to implement a physical layer of a link, and the link couples the adapter to another adapter via the PHY device. The second interface includes a data channel to communicate the link layer data over the physical layer, and a sideband channel to communicate sideband messages between the adapter and the other adapter over the physical layer. The adapter is to implement a logical PHY for the link.

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, are described for performing asymmetric data communication at a host-device interface of a system. The methods include identifying devices coupled to a host of the system and generating a system topology that identifies a connectivity of the devices and identifies bus lanes that enable data transfers at the system. The host determines that a first connection between the host and a first device of the multiple devices has an asymmetric bandwidth requirement. The host configures a set of bus lanes of a data bus connecting the first device and the host to allocate a different number of the bus lanes to data egress from the host than to data ingress to the host. The bus lanes are configured to allocate the differing number of bus lanes based on the asymmetric bandwidth requirement of the first connection.